MT4LC8M8P4

Features:

• Single +3.3V ±0.3V power supply
• Industry-standard x8 pinout, timing, functions, and packages
• 12 row, 11 column addresses (C2) or 13 row, 10 column addresses (P4)
• High-performance CMOS silicon-gate process
• All inputs, outputs and clocks are LVTTLcompatible
• Extended Data-Out (EDO) PAGE MODE access
• 4,096-cycle CAS#-BEFORE-RAS# (CBR) REFRESH distributed across 64ms
• Optional self refresh (S) for low-power data retention


Pinout




Specifications

Voltage on V_CC Relative to V_SS .................................................................... -1V to +4.6V
Voltage on NC, Inputs or I/O Pins Relative to V_SS ....................................... -1V to +4.6V
Operating Temperature, T_A (ambient) ......................................................... 0°C to +70°C
Storage Temperature (plastic) ..................................................................... -55°C to +150°C
Power Dissipation ........................................................................................ 1W

*Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.


Description

The 8 Meg x 8 DRAM MT4LC8M8P4 is a high-speed CMOS, dynamic random-access memory devices containing 67,108,864 bits and designed to operate from 3V to 3.6V. The MT4LC8M8C2 and MT4LC8M8P4 are functionally organized as 8,388,608 locations containing eight bits each. The 8,388,608 memory locations are arranged in 4,096 rows by 2,048 columns on the C2 version and 8,192 rows by 1,024 columns on the P4 version. During READ or WRITE cycles, each location isuniquely addressed via the address bits. First, the row address of MT4LC8M8P4 is latched by the RAS# signal, then the column address is latched by CAS#. Both devices provide EDOPAGE- MODE operation, allowing for fast successive data operations (READ, WRITE, or READ-MODIFYWRITE) within a given row.

The 8 Meg x 8 DRAM MT4LC8M8P4 must be refreshed periodically in order to retain stored data.