MT4LC16M4G3

Single +3.3V ±0.3V power supply
Industry-standard x4 pinout, timing, functions,and packages
12 row, 12 column addresses (H9) or13 row, 11 column addresses (G3)
High-performance CMOS silicon-gate process
All inputs, outputs and clocks are LVTTL-compat-ible
Extended Data-Out (EDO) PAGE MODE access
Optional self refresh (S) for low-power dataretention
4,096-cycle CAS#-BEFORE-RAS# (CBR) REFRESHdistributed across 64ms

The 16 Meg x 4 DRAM MT4LC16M4G3 is a high-speed CMOS,dynamic random-access memory device containing67,108,864 bits and designed to operate from 3V to3.6V. The MT4LC16M4H9 and MT4LC16M4G3 arefunctionally organized as 16,777,216 locations con-taining 4 bits each. The 16,777,216 memory locationsare arranged in 4,096 rows by 4,096 columns on the H9version and 8,192 rows by 2,048 columns on the G3version. During READ or WRITE cycles, each location isuniquely addressed via the address bits. First, the rowaddress of MT4LC16M4G3 is latched by the RAS# signal, then the column address is latched by CAS#. The device provides EDO-PAGE-MODE operation, allowing for fast successivedata operations (READ, WRITE, or READ-MODIFY-WRITE) within a given row.

The 16 Meg x 4 DRAM MT4LC16M4G3 must be refreshed periodicallyin order to retain stored data.