MT4LC16M4T8

Voltage on V_CC Relative to V_SS ................... -1V to +4.6V
Voltage on NC, Inputs or I/O Pins
      Relative to V_SS ...................................... -1V to +4.6V
Operating Temperature, TA (ambient) .... 0°C to +70°C
Storage Temperature (plastic) .......... -55°C to +150°C
Power Dissipation ..................................................... 1W
*Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

The 16 Meg x 4 DRAMs are high-speed CMOS,dynamic random-access memory devices contain-ing 67,108,864 bits organized in a x4 configuration. The MT4LC16M4A7 and MT4LC16M4T8 are functionally organized as 16,777,216 locations containing four bits each. The 16,777,216 memory locations are arranged in 8,192 rows by 2,048 columns for the MT4LC16M4A7 or 4,096 rows by 4,096 columns for the MT4LC16M4T8.

During READ or WRITE cycles, each location of MT4LC16M4T8 is uniquely addressed via the address bits. First, the row address is latched by the RAS# signal, then the column address by CAS#. Both devices provide FAST-PAGE-MODE operation, allowing for fast successive data operations (READ, WRITE, or READ-MODIFY-WRITE) within a given row.

The MT4LC16M4A7 and MT4LC16M4T8 must be refreshed periodically in order to retain stored data.