MT4LC8M8E1

Features:

• Single +3.3V ±0.3V power supply
• Industry-standard x8 pinout, timing, functions, and packages
• 13 row, 10 column addresses (E1) or 12 row, 11 column addresses (B6)
• High-performance CMOS silicon-gate process
• All inputs, outputs and clocks are LVTTL compatible
• FAST PAGE MODE (FPM) access
• 4,096-cycle CAS#-BEFORE-RAS# (CBR) REFRESH distributed across 64ms
• Optional self refresh (S) for low-power data retention


Pinout




Specifications

Voltage on VCC Relative to VSS ................-1V to +4.6V
Voltage on NC, Inputs or I/O Pins
  Relative to VSS ...................................... -1V to +4.6V
Operating Temperature, TA (ambient) ..0°C to +70°C
Storage Temperature (plastic) ........-55°C to +150°C
Power Dissipation .................................................. 1W


Description

The 8 Meg x 8 DRAMs MT4LC8M8E1 are high-speed CMOS, dynamic random-access memory devices containing 67,108,864 bits organized in a x8 configuration. The 8 Meg x 8 DRAMs are functionally organized as 8,388,608 locations containing eight bits each. The 8,388,608 memory locations are arranged in 8,192 rows by 1,024 columns for the MT4LC8M8E1 or 4,096 rows by 2,048 columns for the MT4LC8M8B6. During READ or WRITE cycles, each location is uniquely addressed via the address bits. First, the row address is latched by theRAS# signal, then the column address by CAS#. MT4LC8M8E1 provide FAST-PAGE-MODE operation, allowing for fast successive data operations (READ, WRITE, or READ-MODIFY-WRITE) within a given row.

The MT4LC8M8E1 and MT4LC8M8B6 must be refreshed periodically in order to retain stored data.