MT4LC4M16F5

The 4 Meg x 16 DRAM is a high-speed CMOS, dynamic random-access memory device containing 67,108,864 bits organized in a x16 configuration. The MT4LC4M16F5 is functionally organized as 4,194,304 locations containing 16 bits each. The 4,194,304 memory locations are arranged in 4,096 rows by 1,024
columns. During READ or WRITE cycles, each location is uniquely addressed via the address bits: 12 rowaddress bits (A0-A11) and 10 column-address bits (A0- A9). In addition, both byte and word accesses of MT4LC4M16F5 are supported via the two CAS# pins (CASL# and CASH#). The CAS# functionality and timing related to address and control functions (e.g., latching column addresses or selecting CBR REFRESH) are such that the internal CAS# signal is determined by the first external CAS# signal (CASL# or CASH#) to transition LOW and the last to transition back HIGH. The CAS# functionality and timing of MT4LC4M16F5 related to driving or latching data are such that each CAS# signal independently controls the associated eight DQ pins.

The row address of MT4LC4M16F5 is latched by the RAS# signal, then the column address by CAS#. The device provides FASTPAGE- MODE operation, allowing for fast successive data operations (READ, WRITE, or READ-MODIFYWRITE) within a given row.

The MT4LC4M16F5 must be refreshed periodically in order to retain stored data.