MT4LC1M16E5

Features:

• JEDEC- and industry-standard x16 timing, functions, pinouts, and packages
• High-performance CMOS silicon-gate process
• Single power supply (+3.3V ±0.3V or 5V ±10%)
• All inputs, outputs and clocks are TTL-compatible
• Refresh modes: RAS#-ONLY, CAS#-BEFORE-RAS# (CBR), HIDDEN; optional self refresh (S)
• BYTE WRITE access cycles
• 1,024-cycle refresh (10 row, 10 column addresses)
• Extended Data-Out (EDO) PAGE MODE access
• 5V-tolerant inputs and I/Os on 3.3V devices


Pinout




Specifications

Voltage on V_CC Pin Relative to V_SS
  3.3V ........................................................................... -1V to +4.6V
  5V .............................................................................. -1V to +7V
Voltage on NC, Inputs or I/O Pins Relative to Vss:
  3.3V ........................................................................... -1V to +5.5V
  5V .............................................................................. -1V to +7V
Operating Temperature
  T_A (commercial) .......................................................... 0ºC to +70ºC
  T_A (extended) ............................................................ -20ºC to +80ºC
Storage Temperature (plastic) ..................................... -55ºC to +150ºC
Power Dissipation ........................................................ 1W
Short Circuit Output Current......................................... 50mA

*Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.


Description

The 1 Meg x 16 MT4LC1M16E5 is a randomly accessed, solid-state memory containing 16,777,216 bits organized in a x16 configuration. The 1 Meg x 16 has both BYTE WRITE and WORD WRITE access cycles via two CAS# pins (CASL# and CASH#). These function like a single CAS# found on other DRAMs in that either CASL# or CASH# will generate an internal CAS#.

The CAS# function and timing of MT4LC1M16E5 are determined by the first CAS# (CASL# or CASH#) to transition LOW and the last CAS# to transition back HIGH. Using only one of the two signals results in a BYTE WRITE cycle. CASL# transitioning LOW selects an access cycle for the lower byte (DQ0-DQ7), and CASH# transitioning LOW selects an access cycle for the upper byte (DQ8-DQ15).

Each bit of MT4LC1M16E5 is uniquely addressed through the 20 address bits during READ or WRITE cycles. These are entered 10 bits (A0-A9) at a time. RAS# is used to latch the first 10 bits and CAS#, the latter 10 bits. The CAS# function also determines whether the cycle will be a refresh cycle (RAS# ONLY) or an active cycle (READ, WRITE or READ-WRITE) once RAS# goes LOW.

The CASL# and CASH# inputs of MT4LC1M16E5 internally generate a CAS# signal that functions like the single CAS# input on other DRAMs. The key difference is each CAS# input (CASL# and CASH#) controls its corresponding eight DQ inputs during WRITE accesses. CASL# controls DQ0-DQ7, and CASH# controls DQ8-DQ15. The two CAS# controls give the 1 Meg x 16 both BYTE READ and BYTE WRITE cycle capabilities.

A logic HIGH on WE#  of MT4LC1M16E5 dictates read mode, while a logic LOW on WE# dictates write mode. During a WRITE cycle, data-in (D) is latched by the falling edge of WE or CAS# (CASL# or CASH#), whichever occurs last. An EARLY WRITE occurs when WE is taken LOW prior to either CAS# falling. A LATE WRITE or READ-MODIFYWRITE occurs when WE falls after CAS# (CASL# or CASH#) was taken LOW. During EARLY WRITE cycles, the data outputs (Q) will remain High-Z, regardless of the state of OE#. During LATE WRITE or READMODIFY- WRITE cycles, OE# of MT4LC1M16E5 must be taken HIGH to disable the data outputs prior to applying input data. If a LATE WRITE or READ-MODIFY-WRITE is attempted while keeping OE# LOW, no WRITE will occur, and the data outputs will drive read data from the accessed location.

The 16 data inputs and 16 data outputs of MT4LC1M16E5 are routed through 16 pins using common I/O. Pin direction is controlled by OE# and WE#.

The 1 Meg x 16 DRAM MT4LC1M16E5 must be refreshed periodically in order to retain stored data.