MT4C4M4B1

The 4 Meg x 4 DRAM MT4C4M4B1 is a randomly accessed, solid- state memory containing 16,777,216 bits organized in a x4 configuration. RAS# is used to latch the row address (first 11 bits for 2K and first 12 bits for 4K). Once the page has been opened by RAS#, CAS# of MT4C4M4B1 is used to latch the column address (the latter 11 bits for 2K and the latter 10 bits for 4K; address pins A10 and A11 are "Don't Care").

READ and WRITE cycles of MT4C4M4B1 are selected with the WE# input. A logic HIGH on WE# dictates read mode, while a logic LOW on WE# dictates write mode. During a WRITE cycle, data-in (D) is latched by the falling edge of WE# or CAS#, whichever occurs last. If WE# goes LOW prior to CAS# going LOW, the output pins remain open (High- Z) until the next CAS# cycle, regardless of OE#.