MT28F200B5

• Five erase blocks:
    16KB/8K-word boot block (protected)
    Two 8KB/4K-word parameter blocks
    Two main memory blocks
• Smart 5 technology (B5):
    5V ±10% V_CC
    5V ±10% V_PP application/production
    programming
    12V ±5% V_PP compatibility production
    programming
• Address access times: 60ns, 80ns
• 100,000 ERASE cycles
• Industry-standard pinouts
• Inputs and outputs are fully TTL-compatible
• Automated write and erase algorithm
• Two-cycle WRITE/ERASE sequence
• Byte- or word-wide READ and WRITE
    (MT28F200B5, 128K x 16/256K x 8)
• Byte-wide READ and WRITE only
    (MT28F002B5, 256K x 8)
• TSOP and SOP packaging options

The MT28F002B5 and MT28F200B5 flash memory incorporate a number of features ideally suited for system firmware. The memory array is segmented into individual erase blocks. Each block may be erased without affecting data stored in other blocks. These memory blocks are read, written and erased with commands to the command execution logic (CEL). The CEL of MT28F200B5 controls the operation of the internal state machine (ISM), which completely controls all WRITE, BLOCK ERASE and VERIFY operations. The ISM protects each memory location from over-erasure and optimizes each memory location for maximum data retention. In addition, the ISM of MT28F200B5 greatly simplifies the control necessary for writing the device in-system or in an external programmer.

The Functional Description provides detailed information on the operation of the MT28F002B5 and MT28F200B5 and is organized into these sections:

• Overview

• Memory Architecture

• Output (READ) Operations

• Input Operations

• Command Set

• ISM Status Register

• Command Execution

• Error Handling

• WRITE/ERASE Cycle Endurance

• Power Usage

• Power-Up