MT28C128564W18

• Stacked die Combo package Includes two 64Mb Flash devices Choice of either one 32Mb or one 64Mb CellularRAM device
• Basic configuration   Flash   Flexible multibank architecture
4 Meg x 16 Async/Page/Burst interface Support for true concurrent operations with no latency  CellularRAM Low-power, high-density design 2 Meg x 16 or 4 Meg x 16 configurations Async/Page
• F_VCC, VCCQ, F_VPP, PS_VCC voltages
1.70V (MIN)/1.95V (MAX) F_VCC, PS_VCC
1.70V (MIN)/2.24V (MAX) VCCQ (W18)
1.70V (MIN)/3.3V(MAX) VCCQ (W30)
1.80V (TYP) F_VPP (in-system PROGRAM/ERASE)
12V ±5% (HV) F_VPP (in-house programming and accelerated programming algorithm [APA] activation)
• Asynchronous access time  Flash/CellularRAM access time: 60ns @ 1.70V VCC
• Page Mode read access (W18/W30)
Interpage read access: 60ns @ 1.70V F_VCC , PS_VCC (W18)
Intrapage read access: 20ns @ 1.70V F_VCC, PS_VCC (W18)
Interpage read access: 70ns @ 1.70V F_VCC , PS_VCC (W30)
Intrapage read access: 22ns @ 1.70V F_VCC, PS_VCC (W30)
• Enhanced suspend options
ERASE-SUSPEND-to-READ within same bank
PROGRAM-SUSPEND-to-READ within same bank
ERASE-SUSPEND-to-PROGRAM within same bank
• Read/Write CellularRAM during program/erase of Flash
• Each Flash contains two 64-bit chip protection registers for security purposes
• Flash PROGRAM/ERASE cycles 100,000 WRITE/ERASE cycles per block
• Cross-compatible command set support Extended command set Common Flash interface (CFI) compliant
• Manufacturer's ID (ManID) Micron® (0x2Ch) Intel® (0x89h)

NOTE:
1. Stresses greater than those listed in Table 6 may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
2. Maximum DC voltage on VPP may overshoot to +14V for periods <20ns.

The MT28C128532W18/W30D and MT28C128564W18/W30D combination Flash and CellularRAM are high-performance, high-density, memory solutions that can significantly improve system performance. The Flash architecture features a multipartition configuration that supports READ-while-PROGRAM/ERASE operations with no latency. A 4Mb partition size enables optimal design flexibility.Two Flash devices are stacked to achieve the 128Mb density. Each Flash die has a dedicated CE# and OE# control, enabling each Flash to be independently selectable.The MT28C128532W18/W30D and MT28C128564W18/W30D stacked Flash devices enable soft protection for blocks, as read only, by configuring soft protection registers with dedicated command sequences. For security purposes, two userprogrammable 64-bit chip protection registers are provided for each Flash device.

The embedded WORD PROGRAM and BLOCK ERASE functions of MT28C128564W18 are fully automated by an on-chip write state machine (WSM). An on-chip device status register can be used to monitor the WSM status and determine the progress of the PROGRAM/ERASE tasks.

Each Flash device MT28C128564W18 has a read configuration register (RCR) that defines how the Flash interacts with the memory bus. For device specifications and additional documentation concerning Flash and CellularRAM features,please refer to the MT28F644W18/W30 data sheet at www.micron.com/flash and the MT28C128564W18 data sheets at http://www.micron.com/cellularram.The CellularRAM architecture features high-speed CMOS, dynamic random-access memories developed for low-power portable applications The CellularRAM device is available in either 32Mb or 64Mb densities.

To operate seamlessly on a burst Flash bus, Cellular-RAM products MT28C128564W18 have incorporated a transparent selfrefresh mechanism. The hidden refresh requires no additional support from the system memory controller and has no significant impact on device read/write performance.

The refresh configuration register (CR) of MT28C128564W18  is used to control how refresh is performed on the DRAM array. These registers are automatically loaded with default settings during power-up and can be updated any time during normal operation. Special attention has been focused on standby current consumption during self-refresh.CellularRAM products include three system-accessible mechanisms used to minimize standby current.

Partial array refresh (PAR) of MT28C128564W18 limits refresh to the portion of the memory array being used. Temperature compensated refresh (TCR) is used to adjust the refresh rate according to the ambient temperature. The refresh rate can be decreased at lower temperatures to minimize current consumption during standby. Deep power down (DPD) halts the REFRESH operation altogether and is used when no vital information is stored in the device. These three refresh mechanisms of MT28C128564W18 are adjusted through the CR.

Please refer to Micron's Web site www.micron.com/flash for the latest MT28F644W18/W30 Flash data sheet and http://www.micron.com/cellularram for the latest MT28C128564W18 CellularRAM data sheet.