Features: • Signale power supply : 3.3V±0.3V• 512 Rows X 512 Column X 12 bits• Fast FIFO (First-In First-Out) Operation• High Speed Asynchronous Serial Access• Read/Write Cycle Time 30 ns/40 ns• Access Time 30 ns/35 ns• Direct Cascading Capability• W...
MSM54V12222A: Features: • Signale power supply : 3.3V±0.3V• 512 Rows X 512 Column X 12 bits• Fast FIFO (First-In First-Out) Operation• High Speed Asynchronous Serial Access• Read/Wri...
SeekIC Buyer Protection PLUS - newly updated for 2013!
268 Transactions
All payment methods are secure and covered by SeekIC Buyer Protection PLUS.
Features: · 1,048,576-word × 1-bit configuration· Single 5 V power supply, ±10% tolerance· Input :...
Features: • 1,048,576-word ´ 16-bit configuration• Single 5 V power supply, ±10%...
Parameter |
Symbol |
Condition |
Rating |
Unit |
Input Output Voltage |
VT |
at Ta = 25°C, Vss |
1.0~4.6 |
V |
Output Current |
IOS |
Ta = 25°C |
50 |
mA |
Power Dissipation |
PD |
Ta = 25°C |
1 |
W |
Operating Temperature |
Topr |
- |
0 ~ 70 |
°C |
Storage Temperature |
Tstg |
- |
55~150 |
°C |
The OKI MSM54V12222A is a high performance 3M bits, 256K X 12 bits, Field Memory especially designed for high-speed serial access applications such as HDTVs, conventional NTSC TVs, VTRs, digital movies and Multi-media systems. MSM54V12222A is a FRAM for wide or low end use as general com modity TVs and VTRs, exclusively. MSM54V12222A is not designed for the other use or high end use asmedical systems, professional graphics systems require long time picture storage, data storage systems and others. More than two MSM54V12222As can be cascaded directly without any delay devices among the MSM54V12222As. ( Cascading of MSM54V12222A provides larger storage depth or a longer delay.)
Each of the 12-bits planes of MSM54V12222A has separate serial write and read ports that employ independent control clocks to support asynchronous read and write operations. Different clock rates are also supported that allow alternate data rates between write and read data streams.
The MSM54V12222A provides high speed FIFO, First-In First-Out, operation without external refreshing:MSM54V12222A refreshes its DRAM storage cells automatically, so that it appears fully static to the users.
Moreover, fully static type memory cells and decoders for serial access enable the serial access operation refresh free, so that serial read and/or write control clock can be halted high or low for any time as long as the power is on. Internal conflicts of any memory access and refreshing operation are prevented by special arbitration logic.
The MSM54V12222A's function is simple like that of a digital delay device whose delay-bit-length is easily set by reset timing. The delay length,number of read delay clocks between write and read, is determined by externally controlled write and read reset timings.