Features: • 65,536-wordx 16-bit configuration• Power supply voltage: 2.7 V to 3.6 V• Fully static operation• Operating temperature range: Ta = 0°C to 70°C• (Input/Output) LVCMOS compatible• 3-state output• Data retention available at power supply voltage 2...
MSM52V1017LL: Features: • 65,536-wordx 16-bit configuration• Power supply voltage: 2.7 V to 3.6 V• Fully static operation• Operating temperature range: Ta = 0°C to 70°C• (Input/Outpu...
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Features: · 1,048,576-word × 1-bit configuration· Single 5 V power supply, ±10% tolerance· Input :...
Features: • 1,048,576-word ´ 16-bit configuration• Single 5 V power supply, ±10%...
• 65,536-word x 16-bit configuration
• Power supply voltage: 2.7 V to 3.6 V
• Fully static operation
• Operating temperature range: Ta = 0°C to 70°C
• (Input/Output) LVCMOS compatible
• 3-state output
• Data retention available at power supply voltage 2 V
• Equal to Mask ROM/OTP in supply pin layout
• Package options:
- 44-pin 400 mil plastic TSOP (Type II) (TSOPII44-P-400-0.80-K) (Product : MSM52V1017LL-xxTS-K) (TSOPII44-P-400-0.80-L) (Product : MSM52V1017LL-xxTS-L) xx indicates speed rank.
Parameter | Symbol | Condition | Rating | Unit |
Power Supply Voltage | VCC | Ta = 25°C, for VSS | 0.5 to 4.6 | V |
Pin Voltage | VT | 0.5* to VCC + 0.5 | V | |
Power Dissipation | PD | Ta = 25°C | 0.7 | W |
Operating Temperature | Topr | - | 0 to 70 | °C |
Storage Temperature | Tstg | - | 55 to 125 | °C |
The MSM52V1017LL is a 65,536-word by 16-bit CMOS static RAM featuring 2.7 V to 3.6 V power supply operation and direct LVCMOS input/output compatibility. Since the circuitry is completely static, external clock and refreshing operations are unnecessary, making this device very easy to use. The MSM52V1017LL can be used in the high-speed operation of an access time 85 ns due to adopting a high-performance CMOS technology and in the very low current consumption of a standby current max. 20 A when there is no chip selection. In addition, the MSM52V1017LL is provided with a chip enable signal (CE) suited to the expansion of a memory capacity, an output enable signal (OE) suited to the I/O bus line control, and a byte select signal (LB, UB) that can independently control the input/output of a lower byte and an upper byte.