DescriptionThe MSM5221GS is a kind of 56 dot static LCD driver which is fabricated by low power CMOS metal gate technology. This LSI includes 56-pin shift register, 56-bit latch and 56-bit LCD driver. The display data, which input to the 56-bit shift register, is shifted to the 56-bit latch by the...
MSM5221GS: DescriptionThe MSM5221GS is a kind of 56 dot static LCD driver which is fabricated by low power CMOS metal gate technology. This LSI includes 56-pin shift register, 56-bit latch and 56-bit LCD drive...
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Features: · 1,048,576-word × 1-bit configuration· Single 5 V power supply, ±10% tolerance· Input :...
Features: • 1,048,576-word ´ 16-bit configuration• Single 5 V power supply, ±10%...
The MSM5221GS is a kind of 56 dot static LCD driver which is fabricated by low power CMOS metal gate technology. This LSI includes 56-pin shift register, 56-bit latch and 56-bit LCD driver. The display data, which input to the 56-bit shift register, is shifted to the 56-bit latch by the LOAD signal. Then the data is output to the LCD panel through the 56-bit LCD driver.
There are some features of MSM5221GS as follows: (1)56 dots static LCD driving capability; (2)simple interface with microcomputer chip (controlled by three input signals); (3)bit-to-bit correspondence between the input and the output; (4)cascade connection capability; (5)LCD driving AC frequency is directly input externally; (6)applicable as an output expander; (7)supply voltage: 3 to 7 V; (8)fully controlled by the software; (9)80-pin plastic QFP (QFP80-P-1420-K); (9)80 pin VI plastic QFP (QFP80-P-1420-VIK).
What comes next is the absolute maximum ratings of MSM5221GS: (1)supply voltage, VDD-VSS: -0.3 to +7 V at Ta=25; (2)input voltage, VI: VSS-0.3 to VDD+0.3 V at Ta=25; (3)storage temperature, Tstg: -55 to +150. Then is about the operating range: (1)supply voltage, VDD-VSS: 3 to 7 V; (2)operating temperature, Top: -40 to +85.
The following is the switching characteristics of MSM5221GS(VDD=5 V±105, Ta=25): (1)propagation delay time, tPHL: 600 ns max; (2)data out delay time, tPLH: 600 ns max; (3)maximum clock frequency, fCL: 1 MHz min at DUTY=50%; (4)clock width, tw(CL): 400 ns min; (5)load width, tw(L): 400 ns min; (6)data setup time, tsetup: 300 ns min; (7)data setup time, thold: 300 ns min.