MSM51V4223C

• Single power supply: 3.0~3.6V
• 512 Rows x512 Column x 4 bits
• Fast FIFO (First-in First-out) operon
• High speed asynchronous serial access
   - Read/Write cycle time 30 ns/40 ns
   - Access time 30 ns/35 ns
• Direct cascading capability
• Write mask function (Input enable control)
• Data skipping function (Output enable control)
• Self refresh (No refresh control is required)
• Package:
   - 18-pin 300 mil plastic DIP (DIP18-P-300-2.54) (Product : MSM51V4223C-xxRS) xx indicates speed rank.

The OKI MSM51V4223C is a high performance 1-Mbit, 256K x 4-bit, Field Memory. It is designed for high-speed serial access applications such as HDTVs, conventional NTSC TVs, VTRs, digital movies and Multi-media systems. It is a FRAM for wide or low end use as general commodity TVs and VTRs, exclusively. The MSM51V4223C is not designed for the other use or high end use in medical systems, professional graphics systems which require long term picture, and data storage systems and others. The 1-Mbit capacity fits one field of a conventional NTSC TV screen and cascaded two MSM51V4223Cs make one frame of the screen: more than two MSM514223Cs can be cascaded directly without any delay devces among the MSM514223Cs. (Cascading of MSM51V4223C provides larger storage depth or a longer delay).

Each of the 4-bit planes has separate serial write and read ports that employ independent control clocks to support asynchronous read and write operations. Different clock rates are also supported that allow alternate data rates between write and read data streams.

The MSM51V4223C provides high speed FIFO, First-In First-Out, operation without external refreshing: it refreshes its DRAM storage cells automatically, so that it appears fully static to the users.

Moreover, fully static type memory cells and decoders for serial access enable refresh free serial access operation, so that serial read and/or write control clock can be halted high or low for any duration as long as the power is on. Internal conflicts of memory access and refreshing operations are prevented by special arbitration logic.

The MSM51V4223C's function is simple, and similar to a digital delay device whose delay-bitlength
is easily set by reset timing. The delay length, number of read delay clocks between write
and read, is determined by externally controlled write and read reset timings.

Additional SRAM serial registers, or line buffers for the initial access of 256 x 4-bit enable high
speed first-bit-access with no clock delay just after the write or read reset timings.

The MSM51V4223C is similar in operation and functionality to OKI 1-Mbit Field Memory
MSM51V4221C besides direct cascade capability. (As for MSM51V4221C operation compatible
2-Mbit Field Memory, OKI has MSM51V8221A as a sister device of MSM51V8222A).

Additionally, the MSM51V4223C has write mask function or input enable function (IE), and readdata
skipping function or output enable function (OE). The differences between write enable
(WE) and input enable (IE), and between read enable (RE) and output enable (OE) are that WE
and RE can stop serial write/read address increments but IE and OE can not stop the increment
when write/read clocking is continuously applied to MSM51V4223C. The input enable (IE)
function allows the user to write into selected locations of the memory only, leaving the rest of the
memory contents unchanged. This facilitate data processing to display a "picture in picture" on
a TV screen.