Features: • 32,768-wordx 8-bit configuration• Power supply voltage: 2.7 V to 3.6 V• Operating temperature range: Ta = 0°C to 70°C• (Input/Output) LVTTL compatible• 3-state output• Data retention available at power supply voltage 2 V• Package options: - 28-...
MSM51V257CL: Features: • 32,768-wordx 8-bit configuration• Power supply voltage: 2.7 V to 3.6 V• Operating temperature range: Ta = 0°C to 70°C• (Input/Output) LVTTL compatible• 3-st...
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Features: · 1,048,576-word × 1-bit configuration· Single 5 V power supply, ±10% tolerance· Input :...
Features: • 1,048,576-word ´ 16-bit configuration• Single 5 V power supply, ±10%...
• 32,768-word x 8-bit configuration
• Power supply voltage: 2.7 V to 3.6 V
• Operating temperature range: Ta = 0°C to 70°C
• (Input/Output) LVTTL compatible
• 3-state output
• Data retention available at power supply voltage 2 V
• Package options:
- 28-pin 600 mil plastic DIP (DIP28-P-600-2.54) (Product : MSM51V257CL-xxRS)
- 28-pin 430 mil plastic SOP (SOP28-P-430-1.27-K) (Product : MSM51V257CL-xxGS-K) xx indicates speed rank.
Parameter | Symbol | Condition | Rating | Unit |
Power Supply Voltage | VCC | Ta = 25°C, for VSS | 0.5 to 4.6 | V |
Pin Voltage | VT | 0.5* to VCC + 0.5 | V | |
Power Dissipation | PD | Ta = 25°C | 1.0 | W |
Operating Temperature | Topr | - | 0 to 70 | °C |
Storage Temperature | Tstg | - | 55 to 150 | °C |
The MSM51V257CL is a 32,768-word by 8-bit CMOS static RAM featuring 2.7 V to 3.6 V power supply operation and direct LVTTL input/output compatibility. Since the circuitry is completely static, external clock and refreshing operations are unnecessary, making this device very easy to use. The MSM51V257CL, which uses NMOS cells and CMOS peripherals, can be used in highspeed operation at 70 ns access time and in the low current consumption of a standby current max. 24 mA when there is no chip selection. The MSM51V257CL's ability to hold the memory contents at 2 V provides a battery back-up. Since the MSM51V257CL is provided with the CS and OE signals, it can connect with outputs of other chips in a wired OR technique, which provides easy memory expansion and bus line control.