MSM518222

• Single power supply : 5 V ±10%
• 512 Rows × 512 Columns × 8 bits
• Fast FIFO (First-In First-Out) operation
• High speed asynchronous serial access
           Read/write cycle time 25 ns/30 ns/40 ns
           Access time 25 ns/25 ns/30 ns
• Direct cascading capability
•Write mask function (Input enable control)
• Data skipping function (Output enable control)
• Self refresh (No refresh control is required)
• Package options :
                 28-pin 400 mil plastic ZIP (ZIP28-P-400-1.27) (Product : MSM518222-xxZS)
                 28-pin 400 mil plastic SOJ (SOJ28-P-400-1.27) (Product : MSM518222-xxJS)
                 28-pin 430 mil plastic SOP (SOP28-P-430-1.27-K) (Product : MSM518222-xxGS-K)
                                                                                                         xx indicates speed rank.

The OKI MSM518222 is a high performance 2-Mbit, 256K ´ 8-bit, Field Memory. It is designed for high-speed serial access applications such as HDTVs, conventional NTSCTVs, VTRs, digital movies and Multi-media systems.  The 2-Mbit capacity fits one field of a conventional NTSCTV screen.  Two  cascaded MSM518222s make one frame of the screen: two or more MSM518222s can be cascaded directly without any delay devices between them.  (Cascading provides larger storage depth or a longer delay).

Each of the 8-bit planes has separate serial write and read ports. These employ independent control clocks to support asynchronous read and write operations.  Different clock rates are also supported, which allow alternate data rates between write and read data streams.

The MSM518222 provides high speed FIFO, First-In First-Out, operation without external refreshing: it refreshes its DRAM storage cells automatically, so that it appears fully static to the users.

Moreover, fully static type memory cells and decoders for serial access enable the refresh free serial access operation, so that serial read and/or write control clock can be halted high or low for any duration as long as the power is on.  Internal conflicts of memory access and refreshing operations are prevented by special arbitration logic.

The MSM518222's function is simple and similar to a digital delay device whose delay-bit-length is easily set by reset timing.  The delay length, and the number of read delay clocks between write and read, is determined by externally controlled write and read reset timings.

Additional SRAM serial registers, or line buffers for the initial access of 256 ´ 8-bit enable high speed first-bit-access with no clock delay just after the write or read reset timings.

The MSM518222 is similar in operation and functionality to OKI 1-Mbit Field Memory MSM514221B, with the addition of cascade capability.  (As for MSM514221B operation compatible 2-Mbit Field Memory, OKI has the MSM518221 which is a sister device of MSM518222).

Additionally, the MSM518222 has a write mask function or input enable function (IE), and read-data skipping function or output enable function (OE).  The differences between write enable (WE) and input enable (IE), and between read enable (RE) and output enable (OE) are that WE and RE can stop serial write/read address increments, but IE and OE cannot stop the increment, when write/read clocking is continuously applied to MSM518222.  The input enable (IE) function allows the user to write into selected locations of the memory only, leaving the rest of the memory contents unchanged.

This facilitates data processing to display a "picture in picture" on a TV screen.