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MSC8103/D

Features: • SC140 Core- Architecture optimized for efficient C/C++ code compilation- Four 16-bit ALUs and two 32-bit AGUs- 1200 DSP MMACS running at 300 MHz- Very low power- Variable-Length Execution Set (VLES) execution model- JTAG/Enhanced OnCE debug port• Communications Processor Mo...

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MSC8103/D: Features: • SC140 Core- Architecture optimized for efficient C/C++ code compilation- Four 16-bit ALUs and two 32-bit AGUs- 1200 DSP MMACS running at 300 MHz- Very low power- Variable-Length Ex...

MSC8103/D Data Sheet

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Part Number:
MSC8103/D
Supply Ability:
5000

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  • 1~5000
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  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

• SC140 Core
- Architecture optimized for efficient C/C++ code compilation
- Four 16-bit ALUs and two 32-bit AGUs
- 1200 DSP MMACS running at 300 MHz
- Very low power
- Variable-Length Execution Set (VLES) execution model
- JTAG/Enhanced OnCE debug port
• Communications Processor Module (CPM)
- Programmable protocol machine using a 32-bit RISC engine
- 155 Mbps ATM interface (including AAL 0/1/2/5)
- 10/100 Mbit Ethernet interface
- Up to four E1/T1 interfaces or one E3/T3 interface and one E1/T1 interface
- HDLC support up to T3 rates, or 256 channels
• 64- or 32-bit Wide Bus Interface
- Support for bursts for high efficiency
- Glueless interface to 60x-compatible bus systems
- Multi-master support
• Programmable Memory Controller
- Control for up to eight banks of external memory
- User-programmable machines (UPM) allowing glueless interface to various memory types (SRAM, DRAM, EPROM, and Flash memory) and other user-definable peripherals
- Dedicated pipelined SDRAM memory interface
• Large internal SRAM
- 256K 16-bit words (512 KB)
- Unified program and data space configurable by the application
- Word and byte addressable
• DMA Controller
- 16 DMA channels, FIFO based, with burst capabilities
- Sophisticated addressing capabilities
• Small Foot Print Package
- 17 mm * 17 mm lidded FC-PBGA package
• Very Low Power Consumption
• Separate power supply for internal logic (1.6 V) and for I/O (3.3 V)
• Enhanced 16-bit Parallel Host Interface (HDI16)
- Supports a variety of microcontroller, microprocessor, and DSP bus interfaces
• Phase-Lock Loops (PLLs)
- System PLL
- CPM DPLLs (SCC and SCM)
• Process Technology
- Uses 0.13 micron copper interconnect process technology


Application

• Third-generation wideband wireless infrastructure systems
• Packet Telephony systems
• Multi-channel modem banks
• Multi-channel xDSL


Description

The Motorola MSC8103 16-bit Digital Signal Processor (DSP) is the first member of th e family of DSPs based on the SC140 DSP core. The MSC8103 is  offered in two core speed levels: 275 and 300 MHz.




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