MSC8102

• Four high-performance StarCore SC140 Digital Signal Processor (DSP) extended cores delivering up to 4400 MMACS using 16 ALUs running at up to 275 MHz, delivering a performance equivalent to a single SC140 core running at 1.1 GHz
• Each extended core includes:
- SC140 core processor.
- Local 224 KB memory space (M1) accessed by the SC140 core with no wait states and atomic access.
- 16 KB, 16-way instruction cache (ICache).
- Programmable interrupt controller (PIC).
- Local interrupt controller (LIC).
• Each SC140 core provides the following:
- Up to 1100 million multiply-accumulates per second (MMACS) using an internal 275 MHz clock at 1.6 V. A multiply-accumulate operation includes a multiply-add instruction with the associated data move and pointer update.
- 4 ALUs per SC140 core.
- 16 data registers, 40 bits each.
- 27 address registers, 32 bits each.
- Hardware support for fractional and integer data types.
- Very rich 16-bit wide orthogonal instruction set.
- Up to six instructions executed in a single clock cycle.
- Variable-length execution set (VLES) that can be optimized for code density and performance.
- IEEE 1149.1 JTAG port.
- Enhanced on-device emulation (EOnCE) module with real-time debugging capabilities.
• Large internal memory spaces (1.440 MB total).
- 224 KB of M1 memory per core (896 KB total).
- 16 KB of ICache per core (64 KB total).
- 476 KB shared memory (M2) operating at the core frequency, accessible from all four SC140 cores via the MQBus, and accessible from the local bus.
- 4 KB boot ROM accessible from all four SC140 cores via the MQBus.
• Internal PLL for generating up to 275 MHz clock for the SC140 cores and up to 91.67 MHz for the 60x-compatible system bus, the local bus and other modules. PLL values are determined at reset based on configuration signal values.
• Very flexible System Interface Unit (SIU) with a memory controller to support a 32/64-bit wide 60x-compatible system bus to access memory and memory-mapped devices:
- Reset controller.
- Real-time clock register.
- Periodic interrupt timer (PIT).
- Hardware bus monitors for the 60x-compatible system bus and local bus.
- Software watchdog timer function.
• Flexible eight-bank memory controller:
- Three user-programmable machines (UPMs), general-purpose chip-select machine (GPCM), and a page-mode SDRAM machine.
- Glueless interface to SRAM, page mode SDRAM, DRAM, EPROM, FLASH and other user-definable peripherals.
- Byte enables for either 64-bit or 32-bit bus width mode.
- Eight external memory banks (banks 07). Two additional memory banks control IPBus peripherals and internal memories (banks 9, 11). Each bank has the following features:
` 32-bit address decoding with programmable mask.
` Variable block sizes (32 KB to 4 GB).
` Selectable memory controller machine.
` Two types of data errors check/correction (on 60x-compatible system bus only): Normal odd/even parity and Read-modify-write (RMW) odd/even parity for single accesses.
` Write-protection capability.
` Control signal generation machine selection on a per-bank basis.
` Flexible chip-select assignment between the 60x-compatible system bus and local bus.
` Support for internal or external masters on the 60x-compatible system bus.
` Data buffer controls activated on a per-bank basis.
` Atomic operation.
` RMW data parity check (on 60x-compatible system bus only).
` Extensive external memory-controller/bus-slave support.
` Parity byte select signal, which enables a fast, glueless connection to RMW-parity devices (on 60x-compatible system bus only).
` Data pipeline to reduce data set-up time for synchronous devices.
• Direct Slave Interface (DSI) that provides a 32/64-bit wide slave host interface. It is part of a dual-system bus architecture shared with the external system bus. The dual architecture allows the DSI data bus to be 32 or 64 bits wide and the system data bus to be 64 or 32 bits wide, respectively. It operates only as a slave device under the control of an external host processor.
• Multi-channel DMA controller:
- 16 time-multiplexed unidirectional channels with infrastructure of 32 channels.
- Services up to four external peripherals.
- Supports DONE or DRACK protocol on two external peripherals.
- Each channel group services 16 internal requests generated by eight internal FIFOs. Each FIFO generates:
` a watermark request to indicate that the FIFO contains data for the DMA to empty and write
to the destination
` a hungry request to indicate that the FIFO can accept more data.
- Priority-based time-multiplexing between channels using 16 internal priority levels
- A flexible channel configuration:
` All channels support all features.
` All channels connect to the 60x-compatible system bus or local bus.
- Flyby transfers in which a single data access is transferred directly from the source to the destination without using a DMA FIFO.
• External interfaces and control modules managed on the internal peripheral bus (IPBus) by an IP master device, including:
- Four time-division multiplexing (TDM) modules, each supporting up to 64 channels (256 channels total)
- RS-232 interface/universal asynchronous receiver/transmitter (UART)
- Two 16-timer modules (32 timers total)
- Eight hardware semaphore registers used by external hosts to control shared resources and ensure data coherency
- Thirty-two general-purpose input/output (GPIO) signals
- Global interrupt controller (GIC) to handle external interrupt functions (input and output)
• Up to four independent TDM modules, each with the following features:
- Either totally independent receive and transmit, each having one data line, one clock line, and one frame sync line or four data lines, one clock and one frame sync that are shared between the transmit and receive.
- Glueless interface to E1/T1 frames and MVIP, SCAS, and H.110 buses.
- Hardware A-law/µ-law conversion
- Up to 50 Mbps per TDM (50 MHz bit clock if one data line is used, 25 MHz if two data lines are used, 12.5 MHz if four data lines are used).
- Up to 256 channels.
- Up to 16 MB per channel buffer (granularity 8 bytes), where A/µ law buffer size is double (granularity 16 byte)
- Receive buffers share one global write offset pointer that is written to the same offset relative to their start address.
- Transmit buffers share one global read offset pointer that is read from the same offset relative to their start address.
- All channels share the same word size.
- Two programmable receive and two programmable transmit threshold levels with interrupt generation that can be used, for example, to implement double buffering.
- Each channel can be programmed to be active or inactive.
- 2-, 4-, 8-, or 16-bit channels are stored in the internal memory as 2-, 4-, 8-, or 16-bit channels, respectively.
- The TDM Transmitter Sync Signal (TxTSYN) can be configured as either input or output.
- Frame Sync and Data signals can be programmed to be sampled either on the rising edge or on the falling edge of the clock.
- Frame sync can be programmed as active low or active high.
- Selectable delay (03 bits) between the Frame Sync signal and the beginning of the frame.
- MSB or LSB first support.
• UART
- Two signals for transmit data and receive data.
- No clock, asynchronous mode.
- Can be serviced either by the SC140 DSP cores or an external host on the 60x-compatible system bus or on the DSI.
- Full-duplex operation.
- Standard mark/space non-return-to-zero (NRZ) format.
- 13-bit baud rate selection.
- Programmable 8-bit or 9-bit data format.
- Separately enabled transmitter and receiver.
- Programmable transmitter output polarity.
- Two receiver wakeup methods:
` Idle line wakeup.
` Address mark wakeup.
- Separate receiver and transmitter interrupt requests.
- Eight flags, the first five can generate interrupt request:
` Transmitter empty.
` Transmission complete.
` Receiver full.
` Idle receiver input.
` Receiver overrun.
` Noise error.
` Framing error.
` Parity error.
- Receiver framing error detection.
- Hardware parity checking.
- 1/16 bit-time noise detection.
- Maximum bit rate 6.25 Mbps.
- Single-wire and loop operations.
• Timers
- Two modules of 16 timers each.
- Each timer has the following features:
` Cyclic or one-shot.
` Input clock polarity control.
` Interrupt request when counting reaches a programmed threshold.
` Pulse or level interrupts.
` Dynamically updated programmed threshold.
` Read counter any time.
- Watchdog mode for the timers that connect to the device.
• Hardware semaphores. Eight coded hardware semaphores, locked by simple write access without need for read-modify-write mechanism.
• General-Purpose I/O (GPIO) port:
- 32 bidirectional signal lines that either serve the peripherals or act as programmable I/O ports.
- Each port can be programmed separately to serve up to two dedicated peripherals, and each port supports open-drain output mode.
• Global Interrupt Controller (GIC):
- Consolidation of chip maskable interrupt and non-maskable interrupt sources and routing toINT_OUT, NMI_OUT, and to the cores.
- Generation of 32 virtual interrupts (eight to each SC140 core) by a simple write access.
- Generation of virtual NMI (one to each SC140 core) by a simple write access.
• Software support, with support from industry-leading third parties:
- Real-Time Operating Systems (RTOS):
` Fully supports MSC8102 device architecture (multi-core, memory hierarchy, ICache, timers, DMA, interrupts, peripherals).
High-performance and deterministic, delivering predictive response time.
Optimized to provide low interrupt latency with high data throughput.
Preemptive and priority-based multitasking.
Fully interrupt/event driven.
Small memory footprint.
Comprehensive set of APIs.
Fully supports MSC8102 DMA, interrupts, and timer schemes.
` Multi-core support:
Enables use of one instance of kernel code all four SC140 cores.
Dynamic and static memory allocation from local memory (M1) and shared memory (M2).
` Distributed system support, enables transparent inter-task communications between tasks running inside the SC140 cores and the other tasks running on devices on the board or remote devices in the network
Messaging mechanism between tasks using mailboxes and semaphores.
Networking support; data transfer between tasks running inside and outside the device using networking protocols.
Includes integrated device drivers for such peripherals as TDM, UART, and external buses.
` Additional features:
Incorporates task debugging utilities integrated with compilers and vendors.
Board support package (BSP) for MSC8102ADS.
- Integrated Development Environment (IDE):
` C/C++ compiler with in-line assembly. Enables the developer to generate highly optimized DSP code. It translates code written in C/C++ into parallel fetch sets and maintains high code density.
` Librarian. Enables the user to create libraries for modularity.
` C libraries. A collection of C/C++ functions for the developer's use.
` Linker. Highly efficient linker to produce executables from object code.
` Debugger. Seamlessly integrated real-time, non-intrusive multi-mode debugger that enables debugging of highly optimized DSP algorithms. The developer can choose to debug in source code, assembly code, or mixed mode.
` Simulator. Device simulation models, enables design and simulation before the hardware arrival.
` Profiler. An analysis tool using a patented Binary Code Instrumentation (BCI) technique that enables the developer to identify program design inefficiencies.
` Version control. CodeWarrior® includes plug-ins for ClearCase, Visual SourceSafe, and CVS.
- Boot options:
` External memory.
` External host.
` UART.
` TDM.
• Power:
- Requires separate power supplies for on-chip logic (1.6 V) and I/O (3.3 V)
- Provides low-power standby modes
- Includes optimized power management circuitry (instruction-dependent, peripheral-dependent, and mode-dependent).
• Packaging:
- 0.8 mm pitch High Temperature Coefficient for Expansion Flip Chip Ceramic Ball-Grid Array (FC-CBGA (HCTE)) or Flip Chip Plastic Ball-Grid Array (FC-PBGA) (pre-production only)
- 431-pin
- 20 mm * 20 mm

Notes: 1. Functional operating conditions are given in Table 2-2.
2. Absolute maximum ratings are stress ratings only, and functional operation at the maximum is not guaranteed. Stress beyond the listed limits may affect device reliability or cause permanent damage.
3. Section 4.1, Thermal Design Considerations, on page 1 includes a formula for computing the chip junction temperature (TJ).

The MSC8102 is a highly integrated system-on- a-chip that combines four StarCore SC140 extended cores with an RS-232 serial interface, four time-division multiplexed (TDM) serial interfaces, thirty-two general-purpose timers, a flexible system interface unit (SIU), and a multi-channel DMA engine. The four extended cores can deliver a total 4400 DSP MMACS performance at 275 MHz.

Each core has four arithmetic logic units (ALUs), internal memory, a write buffer, and two interrupt controllers. The MSC8102 targets high-bandwidth highly computational DSP applications and is optimized for wireless transcoding and packet telephony as well as high-bandwidth base station applications. The MSC8102 delivers enhanced performance while maintaining low power dissipation and greatly reduces system cost.