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MSC8101

Features: • SC140 core - Architecture optimized for efficient C/C++ code compilation - Four 16-bit ALUs and two 32-bit AGUs - 1200 DSP MMACS running at 300 MHz - Very low power dissipation - Variable-length execution set (VLES) execution model - JTAG/Enhanced OnCE debug port• Communica...

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MSC8101: Features: • SC140 core - Architecture optimized for efficient C/C++ code compilation - Four 16-bit ALUs and two 32-bit AGUs - 1200 DSP MMACS running at 300 MHz - Very low power dissipation - V...

MSC8101 Data Sheet

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Part Number:
MSC8101
Supply Ability:
5000

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  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/11/26

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Product Details

Description



Features:

• SC140 core
   - Architecture optimized for efficient C/C++ code compilation
   - Four 16-bit ALUs and two 32-bit AGUs
   - 1200 DSP MMACS running at 300 MHz
   - Very low power dissipation
   - Variable-length execution set (VLES) execution model
   - JTAG/Enhanced OnCE debug port
• Communications processor module (CPM)
   - Programmable protocol machine using a 32-bit RISC engine
   - 155 Mbps ATM interface (including AAL 0/1/2/5)
   - 10/100 Mbit Ethernet interface
   - Up to four E1/T1 interfaces or one E3/T3 interface and one E1/T1 interface
   - HDLC support up to T3 rates, or 256 channels
• 64- or 32-bit wide bus interface
   - Support for bursts for high efficiency
   - Glueless interface to 60x-compatible bus systems
   - Multi-master support
• Enhanced filter coprocessor (EFCOP)
   - Independently and concurrently executes long filters (such as echo cancellation)
   - Runs at 250/275/300 MHz and provides 250/275/300 MMACS performance
• Programmable memory controller
   - Control for up to eight banks of external memory
   - User-programmable machines (UPM) allowing glueless interface to various memory types (SRAM, DRAM,
       EPROM, and Flash memory) and other user-definable peripherals
   - Dedicated pipelined SDRAM memory interface
• Large internal SRAM
   - 256K 16-bit words (512 KB)
   - Unified program and data space configurable by the application
   - Word and byte addressable
• DMA controller
   - 16 DMA channels, FIFO based, with burst capabilities
   - Sophisticated addressing capabilities
• Small foot print package
   - 17 mm * 17 mm lidded FC-PBGA package
• Very low power consumption
   - Separate power supply for internal logic (1.6 V) and for I/O (3.3 V)
• Enhanced 16-bit parallel host interface (HDI16)
   - Supports a variety of microcontroller, microprocessor, and DSP bus interfaces
• Phase-lock loops (PLLs)
   - System PLL
   - CPM DPLLs (SCC and SCM)
• Process technology
   - 0.13 micron copper interconnect process technology


Specifications

Rating
 
Symbol
 
Value
 
Unit
 
Core supply voltage3 
VDD
 
0.2 to 1.7
 
V
 
PLL supply voltage3 
VCCSYN
 
0.2 to 1.7
 
V
 
I/O supply voltage3 
VDDH
 
0.2 to 3.6
 
V
 
Input voltage3 
VIN
 
(GND  0.2) to 3.6
 
V
 
Maximum operating temperature range4 
TJ
 
40 to 120
 
°C
 
Storage temperature range
 
TSTG
 
55 to +150
 
°C

Notes: 1. Functional operating conditions are given in Table 2-2.

             2. Absolute maximum ratings are stress ratings only, and functional operation at   the maximum is not guaranteed. Stress beyond the listed limits may affect device reliability or cause permanent damage.

3. The input voltage must not exceed the I/O supply VDDH by more than 2.5 V at any time, including during power-on reset. In turn, VDDH can exceed VDD/VCCSYN by more than 3.3 V during power-on reset, but for no more than 100 ms. VDDH should not exceed VDD/VCCSYN by more than 2.1 V during normal operation. VDD/VCCSYN must not exceed VDDH by more than 0.4 V at any time, including during power-on reset. See Section 4.2, Electrical Design Considerations, on page 4-1 for more information.

4. Section 4.1, Thermal Design Considerations, on page 4-1 includes a formula for computing the chip junction temperature (TJ).



Description

The Freescale MSC8101 DSP is a very versatile device that integrates the high-performance SC140 four-ALU (arithmetic logic unit) DSP core along with 512 KB of internal memory, a communications processor module (CPM), a 64-bit bus, a very flexible System Integration Unit (SIU), and a 16-channel DMA engine on a single device. With its four-ALU core, the MSC8101 can execute up to four multiply-accumulate (MAC) operations in a single clock cycle. The MSC8101 CPM is a 32- bit RISC-based communications protocol engine that can network to time-division multiplexed (TDM) highways, Ethernet, and asynchronous transfer mode (ATM) backbones. The MSC8101 60x-compatible bus interface facilitates its connection to multi-master system architectures. The very large internal memory, 512 KB, reduces the need for external program and data memories. The MSC8101 offers 1500 DSP MMACS (1200 core and 300 EFCOP) performance using an internal 300 MHz clock with a 1.6 V core and independent 3.3 V input/output (I/O).


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