MPC860SAD

• ATM support
- Compliant with ATM forum UNI 4.0 specification
- Cell processing up to 5070 Mbps at 50-MHz system clock
- Cell multiplexing/demultiplexing
- Support of AAL5 and AAL0 protocols on a per-VC basis
(AAL0 support enables OAM and software implementation of other protocols)
- ATM pace control (APC) scheduler, providing:
Direct support of constant bit rate (CBR)
Direct support of unspecified bit rate (UBR)
Control mechanisms enabling software support of available bit rate (ABR)
- Support for two types of physical interfaces
UTOPIA
Byte-aligned serial (e.g. T1/E1/ADSL)
- UTOPIA-mode ATM supports:
UTOPIA level 1 master with cell-level handshake
Multi-PHY (up to 4 physical layer devices)
Connection to 25 Mbps, 51 Mbps, or 155 Mbps framers
UTOPIA clock rates of 1:2 or 1:3 system clock rates
- Serial-mode ATM connection supports:
Transmission convergence (TC) function for T1/E1/ADSL lines
Cell delineation
Cell payload scrambling/descrambling
Automatic idle/unassigned cell insertion/stripping
Header error control (HEC) generation, checking, and statistics
Glueless interface to Motorola CopperGold ADSL transceiver
- Receive VP/VC connection lookup mechanisms, including:
Internal sequential lookup table supporting up to 32 connections
Support for up to 64K connections using external memory via address compression or content-addressable memory (CAM)
- Independent transmit/receive buffer descriptor ring data structures for each connection
- Interrupt report per channel using exception queue
- Supports 53-byte or up to 64-byte (expanded) ATM cells
- AAL5 segmentation and reassembly (SAR) features for segmentation
Segment CPCS_PDU directly from system memory
CPCS_PDU padding
CRC32 generation
Automatic last cell marking (in PTI field of cell header)
Automatic CS_UU, CPI, and LENGTH insertion in last cell
- AAL5 segmentation and reassembly (SAR) features for reassembly:
Reassembles CPCS_PDU directly into system memory
Removes CPCS_PDU padding
CRC32 checking
CS_UU, CPI, and LENGTH reporting
CLP and congestion reporting
Interrupts per buffer or per message
Error reporting, including CRC, length mismatch, message abort
- AAL0 features for transmit include the following:
Transmits user-defined cell from transmit emory buffer
Automatic HEC generation
Optional CRC10 insertion
- AAL0 features for receive include the following:
Copies entire cell into receive memory buffer
Provides interrupt per cell
Optional CRC10 checking
• Embedded MPC860SAR core with 66 MIPS at 50 MHz (using Dhrystone 2.1)
- Single issue, 32-bit version of the embedded MPC860SAR core (fully compatible with PowerPC user instruction set architecture definition) with 32- x 32-bit fixed-point registers
Performs branch folding and branch prediction with conditional prefetch, but without
conditional execution
4-Kbyte data cache and 4-Kbyte instruction cache, each with an MMU
Instruction and data caches are two-way, set associative, physical address, 4-word line burst, least-recently used (LRU) replacement algorithm, lockable on-line granularity
Memory management units (MMUs) with 32-entry translation lookaside buffers (TLBs) and fully-associative instruction and data TLBs
MMUs support multiple page sizes of 4 Kbytes, 16 Kbytes, 256 Kbytes, 512 Kbytes, and
8 Mbytes; 16 virtual address spaces and 8 protection groups
- Advanced on-chip emulation debug mode
- Data bus dynamic bus sizing for 8-, 16-, and 32-bit buses
- Thirty-two address lines
- Completely static design (0-MHz to 50-MHz operation)
• System integration unit (SIU)
- Hardware bus monitor
- Spurious interrupt monitor
- Software watchdog
- Periodic interrupt timer
- Low-power stop mode
- Clock synthesizer
- decrementer defined by the PowerPC Architecture
- Time base and real-time clock defined by the PowerPC Architecture
- Reset controller
- IEEE 1149.1 test access port (JTAG)
• Memory controller (eight banks)
- Contains complete dynamic random-access memory (DRAM) controller
- Each bank can be a chip-select or RAS to support a DRAM bank
- Up to 15 wait states programmable per memory bank
- Glueless interface to DRAM single in-line memory modules (SIMMs), synchronous DRAM (SDRAM), static random-access memory (SRAM), electrically programmable read-only memory (EPROM), Flash EPROM, etc.
- DRAM controller programmable to support most size and speed memory interfaces
- Four CAS lines, four WE lines, and one OE line
- Boot chip-select available at reset (options for 8-, 16-, or 32-bit memory)
- Variable block sizes, 32 Kbyte to 256 Mbyte
- Selectable write protection
- On-chip bus arbitration logic
• General-purpose timers
- Four 16-bit timers or two 32-bit timers
- Gate mode can enable/disable counting
- Interrupt can be masked on reference match and event capture
• Interrupts
- Seven external interrupt request (IRQ) lines
- Twelve-port pins with interrupt capability
- Sixteen internal interrupt sources
- Programmable priority between SCCs
- Programmable highest-priority request
• PCMCIA interface
- Master (socket) interface, release 2.1 compliant
- Supports two independent PCMCIA sockets
- Supports eight memory or I/O windows
• Communications processor module (CPM)
- Supports all functionality and performance of MPC860MH
- RISC controller
- Communication specific commands (e.g., graceful stop transmit, close receive buffer descriptor, RxBD)
- Up to 384 buffer descriptors
- Supports continuous mode transmission and reception on all serial channels
- Up to 5 Kbytes of dual-port RAM
- Sixteen serial DMA (SDMA) channels
- Three parallel I/O registers with open-drain capability
• Four baud rate generators
- Independent and can be connected to any serial communication controller (SCC) or serial management controller (SMC)
- Allow changes during operation
- Autobaud support option
• Four SCCs (serial communication controllers)
- QMC microcode for protocol processing of 64 time-division multiplexed channels
- Ethernet/IEEE 802.3 on SCC14, supporting full 10-Mbps operation
- HDLC/SDLC™ (all channels supported at 2 Mbps)
- HDLC bus (implements an HDLC-based local area network (LAN))
- Asynchronous HDLC to support PPP (point-to-point protocol)
- AppleTalk™
- Universal asynchronous receiver transmitter (UART)
- Synchronous UART
- Serial infrared (IrDA)
- Binary synchronous communication (BISYNC)
- Totally transparent (bit streams)
- Totally transparent (frame based with optional cyclic redundancy check (CRC))
• QUICC multichannel controller (QMC) microcode features
- Up to 64 independent communication channels on a single SCC
- Arbitrary mapping of 031 channels to any of 031 TDM time slots
- Supports either transparent or HDLC protocols for each channel
- Independent Tx/Rx buffer descriptors and event/interrupt reporting for each channel
- Running QMC microcode independently on multiple SCCs allows even more channels (for example, 64 at 50-MHz system frequency)
• Two serial management controllers (SMCs)
- UART
- Transparent
- General circuit interface (GCI) controller
- Can be connected to the time-division-multiplexed (TDM) channels
• One serial peripheral interface (SPI)
- Supports master and slave modes
- Supports multimaster operation on the same bus
• One I2C® (interprocessor-integrated circuit) port
- Supports master and slave modes
- Supports multimaster environment
• Time slot assigner
- Allows SCCs and SMCs to run in multiplexed and/or nonmultiplexed operation
- Supports T1, CEPT, PCM highway, ISDN basic rate, ISDN primary rate, user-defined
- 1- or 8-bit resolution
- Allows independent transmit and receive routing, Frame Syncs, clocking
- Allows dynamic changes
- Can be internally connected to six serial channels (four SCCs and two SMCs)
• Parallel interface port
- Centronics™ interface support
- Supports fast connection between compatible ports on MPC860 or MC68360
• Low-power support
- Full-on: all units fully powered
- Doze: core functional units disabled except time base decrementer, PLL, memory controller, real-time clock, and communication processor module in low-power standby
- Sleep: all units disabled except real-time clock and periodic interrupt timer. PLL is active for fast wake-up.
- Deep-sleep: all units disabled including PLL, except real-time clock and periodic interrupt timer
- Low-power stop: to provide lower power dissipation
• Debug interface
- Eight comparators: four operate on instruction address, two operate on data address, and two operate on data
- Supports = ¹ < >conditions
- Each watchpoint can generate a breakpoint internally
• 3.3-V operation with 5-V TTL compatibility
• 357-pin ball grid array (BGA) package

The MPC860SAR ATM communication controller is an enhanced version of the MPC860 PowerQUICC™ family. In addition to all existing MPC860MH capabilities, the MPC860SAR includes support for asynchronous transfer mode (ATM).

ATM MPC860SAR support includes all ATM layer functions and some AAL functions, including segmentation and reassembly (SAR) for AAL5. The 860SAR also supports reception and transmission of raw ATM cells directly to and from memory (also known as AAL0), enabling other AAL protocols to be supported in software.

ATM MPC860SAR traffic types directly supported include constant bit rate (CBR) and unspecified bit rate (UBR), with a flexible hardware scheduler enabling implementation of other traffic types in software, such as available bit rate (ABR).

The physical interface of MPC860SAR can be accomplished with the 860SAR by two methods. The first method is via a standard UTOPIA port. The second method is serially, via any of the serial communication controllers (SCCs) of the 860SAR. In addition to the ATM layer and AAL layer functionality, the 860SAR also provides transmission convergence (TC) sublayer functionality, modeled after the TC mapping of ATM cells into T1/E1 frames. Thus, the MPC860SAR can receive any serial ATM data stream with byte-aligned synchronization, including T1, E1, and ADSL.

Like the other MPC860 devices, the MPC860SAR can be used in a variety of controller applications, excelling particularly in communications and networking products that provide WAN to LAN functionality. These include routers, ATM line card controllers, residential broadband network interface units, and ADSL modem and infrastructure applications. The integration of the high-performance MPC860 core and ATM SAR in the 860SAR also enables the design of an ATM switch controller in a single part.

The MPC860SAR integrates two separate processing blocks, common with all MPC860 devices. These are:
• A high-performance core which can be used as a general-purpose processor for application programming
• A RISC engine embedded in the communication processor module (CPM) which is designed to provide the communications protocol processing provided by the MPC860.