Features: The following is a list of the main features of the MPC801:• Embedded PowerPC core with 52 MIPS at 40 MHz (using Dhrystone 2.1)• Single-issue, 32-bit version of the embedded PowerPC core (fully compatible with the PowerPC User Instruction Set Architecture (Book I)) with 32* 3...
MPC801: Features: The following is a list of the main features of the MPC801:• Embedded PowerPC core with 52 MIPS at 40 MHz (using Dhrystone 2.1)• Single-issue, 32-bit version of the embedded Po...
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The MPC801 device is specifically designed to be a general-purpose, low-cost entry point to the embedded PowerPC Family at Motorola. The device excels in applications that require the performance of a single-issue PowerPC core with moderate amounts of data and instruction cache. It can support alternate bus masters in addition to providing all the basic features of glueless memory connections, but does not provide a wealth of serial connectivity. Instead, it supplies simple UART serial channels as well as I2C and SPI channels for onboard communication to other peripheral chips.
The MPC801 excels in low-power and portable applications due to its expansive power-down modes. In addition, the normal operation current is low. The MPC801 is ideal for applications where a significant portion of the user's added value is in peripherals or ASICs and a low-cost general-purpose CPU is required. The programmable flexibility of the memory controller ensures that the board design can accommodate future memory types without hardware changes, thus enabling the ASIC to concentrate on other system goals