MPC859DSL

• Embedded single-issue, 32-bit MPC8xx core (implementing the PowerPC architecture) with thirty-two 32-bit general-purpose registers (GPRs)
- The core performs branch prediction with conditional prefetch, without conditional execution
- 4- or 8-Kbyte data cache and 4- or 16-Kbyte instruction cache (see Table 1-1).
16-Kbyte instruction cache (MPC866P) is four-way, set-associative with 256 sets;4-Kbyte instruction cache(MPC866T, MPC859T, and MPC859DSL) is two-way, set-associative with 128 sets.
8-Kbyte data cache (MPC866P) is two-way, set-associative with 256 sets; 4-Kbyte data cache(MPC866T, MPC859T, and MPC859DSL) is two-way, set-associative with 128 sets.
Cache coherency for both instruction and data caches is maintained on 128-bit (4-word) cache blocks.
Caches are physically addressed, implement a least recently used (LRU) replacement algorithm, and are lockable on a cache block basis.
- MMUs with 32-entry TLB, fully associative instruction and data TLBs
- MMUs support multiple page sizes of 4, 16, and 512 Kbytes, and 8 Mbytes; 16 virtual address spaces and 16 protection groups
- Advanced on-chip-emulation debug mode

1 The power supply of the device must start its ramp from 0.0 V.
2 Functional operating conditions are provided with the DC electrical specifications in Table 6-6. Absolute maximum ratings are stress ratings only; functional operation at the maxima is not guaranteed. Stress beyond those listed may affect device reliability or cause permanent damage to the device. See Section Part VIII, "Power Supply and Power Sequencing". Caution: All inputs that tolerate 5 V cannot be more than 2.5 V greater than VDDH. This restriction applies to power-up and normal operation (that is, if the MPC866/859T/859DSL is unpowered, a voltage greater than 2.5 V must not be applied to its inputs).