MPC852T

The following list summarizes the key MPC852T features:
• Embedded MPC8xx core up to 100 MHz
• Maximum frequency operation of the external bus is 66 MHz
- The 50 MHz / 66 MHz core frequencies support both 1:1 and 2:1 modes.
- The 80 MHz / 100 MHz core frequencies support 2:1 mode only.
• Single-issue, 32-bit core (compatible with the PowerPC architecture definition) with 32 32-bit general-purpose registers (GPRs)
- The core performs branch prediction with conditional prefetch, without conditional execution.
- 4-Kbyte data cache and 4-Kbyte instruction cache
4-Kbyte instruction cache is two-way, set-associative with 128 sets.
4-Kbyte data cacheis two-way, set-associative with 128 sets.
Cache coherency for both instruction and data caches is maintained on 128-bit (4-word) cache blocks.
Caches are physically addressed, implement a least recently used (LRU) replacement algorithm, and are lockable on a cache block basis.
- MMUs with 32-entry TLB, fully associative instruction, and data TLBs
- MMUs support multiple page sizes of 4, 16, and 512 Kbytes, and 8 Mbytes; 16 virtual address spaces, and 16 protection groups
• Up to 32-bit data bus (dynamic bus sizing for 8, 16, and 32 bits)
• 32 address lines
• Memory controller (eight banks)
- Contains complete dynamic RAM (DRAM) controller
- Each bank can be a chip select or RAS to support a DRAM bank
- Up to 30 wait states programmable per memory bank
- Glueless interface to DRAM, SIMMS, SRAM, EPROMs, Flash EPROMs, and other memory devices
- DRAM controller-programmable to support most size and speed memory interfaces
- Four CAS lines, four WE lines, and one OE line
- Boot chip-select available at reset (options for 8-, 16-, or 32-bit memory)
- Variable block sizes (32 Kbytes256 Mbytes)
- Selectable write protection
- On-chip bus arbitration logic
• Fast Ethernet Controller (FEC)
• General-purpose timers
- Two 16-bit timers or one 32-bit timer
- Gate mode can enable or disable counting.
- Interrupt can be masked on reference match and event capture.
• System integration unit (SIU)
- Bus monitor
- Software watchdog
- Periodic interrupt timer (PIT)
- Clock synthesizer
- Decrementer and time base
- Reset controller
- IEEE 1149.1 test access port (JTAG)
• Interrupts
- Seven external interrupt request (IRQ) lines
- Seven port pins with interrupt capability
- Eighteen internal interrupt sources
- Programmable priority between SCCs
- Programmable highest-priority request
• Communications processor module (CPM)
- RISC controller
- Communication-specific commands (for example, GRACEFUL STOP TRANSMIT, ENTER HUNT MODE, and RESTART TRANSMIT)
- Supports continuous mode transmission and reception on all serial channels
- 8-Kbytes of dual-port RAM
- 8 serial DMA (SDMA) channels
- Three parallel I/O registers with open-drain capability
• Two baud rate generators
- Independent (can be connected toany SCC3/4 or SMC1)
- Allows changes during operation
- Autobaud support option
• Two SCCs (serial communication controllers)
- Ethernet/IEEE 802.3 optional on SCC3 & SCC4, supporting full 10-Mbps operation
- HDLC/SDLC
- HDLC bus (implements an HDLC-based local area network (LAN))
- Universal asynchronous receiver transmitter (UART)
- Totally transparent (bit streams)
- Totally transparent (frame-based with optional cyclic redundancy check (CRC))
• One SMC (serial management channels)
- UART
• One SPI (serial peripheral interface)
- Supports master and slave modes
- Supports multimaster operation on the same bus
• PCMCIA interface
- Master (socket) interface, release 2.1 compliant Debug interface
- Eight comparators: four operate on instruction address, two operate on data address, and two operate on data
- Supports conditions: = < >
- Each watchpoint can generate a break point internally.
• Normal high and normal low power modes to conserve power
• 1.8 V Core and 3.3 V I/O operation with 5-V TTL compatibility. Refer to Table 5 for a listing of the 5-V Tolerant pins.

The MPC852T PowerQUICCTM is a 0.18-micron derivative of the MPC860 PowerQUICC family, and can operate up to 100 MHz on the MPC8xx core with a 66-MHz external bus. The MPC852T has a 1.8 V core and a 3.3 V I/O operation with 5-V TTL compatibility. The MPC852T integrated communications controller is a versatile one-chip integrated microprocessor and peripheral combination that can be used in a variety of controller applications. It particularly excels in Ethernet control applications, including CPE equipment, Ethernet routers and hubs, VoIP clients, and WiFi access points.

The MPC852T is a PowerPC architecture-based derivative of the Motorola MPC860 Quad Integrated Communications Controller (PowerQUICC). The CPU on it is the MPC8xx core, a 32-bit microprocessor that implements the PowerPC architecture, incorporating memory management units (MMUs) and instruction and data caches. The MPC852T is the subset of this family of devices.