MPC850EC

The following list summarizes the main features of the MPC850:
• Embedded single-issue, 32-bit MPC8xx core (implementing the PowerPC architecture) with thirty-two 32-bit general-purpose registers (GPRs)
- Performs branch folding and branch prediction with conditional prefetch, but without conditional execution
- 2-Kbyte instruction cache and 1-Kbyte data cache (Harvard architecture)
Caches are two-way, set-associative
Physically addressed
Cache blocks can be updated with a 4-word line burst
Least-recently used (LRU) replacement algorithm
Lockable one-line granularity
- Memory management units (MMUs) with 8-entry translation lookaside buffers (TLBs) and fully-associative instruction and data TLBs
- MMUs support multiple page sizes of 4 Kbytes, 16 Kbytes, 256 Kbytes, 512 Kbytes, and 8 Mbytes; 16 virtual address spaces and eight protection groups
• Advanced on-chip emulation debug mode
• Data bus dynamic bus sizing for 8, 16, and 32-bit buses
- Supports traditional 68000 big-endian, traditional x86 little-endian and modified little-endian memory systems
- Twenty-six external address lines
• Completely static design (080 MHz operation)
• System integration unit (SIU)
- Hardware bus monitor
- Spurious interrupt monitor
- Software watchdog
- Periodic interrupt timer
- Low-power stop mode
- Clock synthesizer
- Decrementer, time base, and real-time clock (RTC) from the PowerPC architecture
- Reset controller
- IEEE 1149.1 test access port (JTAG)
• Memory controller (eight banks)
- Glueless interface to DRAM single in-line memory modules (SIMMs), synchronous DRAM (SDRAM), static random-access memory (SRAM), electrically programmable read-only memory (EPROM), flash EPROM, etc.
- Memory controller programmable to support most size and speed memory interfaces
- Boot chip-select available at reset (options for 8, 16, or 32-bit memory)
- Variable block sizes, 32 Kbytes to 256 Mbytes
- Selectable write protection
- On-chip bus arbiter supports one external bus master
- Special features for burst mode support
• General-purpose timers
- Four 16-bit timers or two 32-bit timers
- Gate mode can enable/disable counting
- Interrupt can be masked on reference match and event capture
• Interrupts
- Eight external interrupt request (IRQ) lines
- Twelve port pins with interrupt capability
- Fifteen internal interrupt sources
- Programmable priority among SCCs and USB
- Programmable highest-priority request
• Single socket PCMCIA-ATA interface
- Master (socket) interface, release 2.1 compliant
- Single PCMCIA socket
- Supports eight memory or I/O windows
• Communications processor module (CPM)
- 32-bit, Harvard architecture, scalar RISC communications processor (CP)
- Protocol-specific command sets (for example, GRACEFUL STOP TRANSMIT stops transmission after the current frame is finished or immediately if no frame is being sent and CLOSE RXBD closes the receive buffer descriptor)
- Supports continuous mode transmission and reception on all serial channels
- Up to 8 Kbytes of dual-port RAM
- Twenty serial DMA (SDMA) channels for the serial controllers, including eight for the four USB endpoints
- Three parallel I/O registers with open-drain capability
• Four independent baud-rate generators (BRGs)
- Can be connected to any SCC, SMC, or USB
- Allow changes during operation
- Autobaud support option
• Two SCCs (serial communications controllers)
- Ethernet/IEEE 802.3, supporting full 10-Mbps operation
- HDLC/SDLC™ (all channels supported at 2 Mbps)
- HDLC bus (implements an HDLC-based local area network (LAN))
- Asynchronous HDLC to support PPP (point-to-point protocol)
- AppleTalk®
- Universal asynchronous receiver transmitter (UART)
- Synchronous UART
- Serial infrared (IrDA)
- Totally transparent (bit streams)
- Totally transparent (frame based with optional cyclic redundancy check (CRC))
• QUICC multichannel controller (QMC) microcode features
- Up to 64 independent communication channels on a single SCC
- Arbitrary mapping of 031 channels to any of 031 TDM time slots
- Supports either transparent or HDLC protocols for each channel
- Independent TxBDs/Rx and event/interrupt reporting for each channel
• One universal serial bus controller (USB)
- Supports host controller and slave modes at 1.5 Mbps and 12 Mbps
• Two serial management controllers (SMCs)
- UART
- Transparent
- General circuit interface (GCI) controller
- Can be connected to the time-division-multiplexed (TDM) channel
• One serial peripheral interface (SPI)
- Supports master and slave modes
- Supports multimaster operation on the same bus
• One I2C® (interprocessor-integrated circuit) port
- Supports master and slave modes
- Supports multimaster environment
• Time slot assigner
- Allows SCCs and SMCs to run in multiplexed operation
- Supports T1, CEPT, PCM highway, ISDN basic rate, ISDN primary rate, user-defined
- 1- or 8-bit resolution
- Allows independent transmit and receive routing, frame syncs, clocking
- Allows dynamic changes
- Can be internally connected to four serial channels (two SCCs and two SMCs)
• Low-power support
- Full high: all units fully powered at high clock frequency
- Full low: all units fully powered at low clock frequency
- Doze: core functional units disabled except time base, decrementer, PLL, memory controller, real-time clock, and CPM in low-power standby
- Sleep: all units disabled except real-time clock and periodic interrupt timer. PLL is active for fast wake-up
- Deep sleep: all units disabled including PLL, except the real-time clock and periodic interrupt timer
- Low-power stop: to provide lower power dissipation
- Separate power supply input to operate internal logic at 2.2 V when operating at or below 25 MHz
- Can be dynamically shifted between high frequency (3.3 V internal) and low frequency (2.2 V internal) operation
• Debug interface
- Eight comparators: four operate on instruction address, two operate on data address, and two operate on data
- The MPC850 can compare using the =,, <, and > conditions to generate watchpoints
- Each watchpoint can generate a breakpoint internally
• 3.3-V operation with 5-V TTL compatibility on all general purpose I/O pins.

1 Functional operating conditions are provided with the DC electrical specifications in Table 5. Absolute maximum ratings are stress ratings only; functional operation at the maxima is not guaranteed. Stress beyond those listed may affect device reliability or cause permanent damage to the device.

CAUTION: All inputs that tolerate 5 V cannot be more than 2.5 V greater than the supply voltage. This restriction pplies to power-up and normal operation (that is, if the MPC850 is unpowered, voltage greater than 2.5 V must not e applied to its inputs).

2 The MPC850, a high-frequency device in a BGA package, does not provide a guaranteed maximum ambient emperature. Only maximum junction temperature is guaranteed. It is the responsibility of the user to consider power dissipation and thermal management. Junction temperature ratings are the same regardless of frequency rating of the device.

The MPC850 is a versatile, one-chip integrated microprocessor and peripheral combination that can be used in a variety of controller applications, excelling particularly in communications and networking products. The MPC850, which includes support for Ethernet, is specifically designed for cost-sensitive, remote-access, and telecommunications applications. It is provides functions similar to the MPC860, with system enhancements such as universal serial bus (USB) support and a larger (8-Kbyte) dual-port RAM.

In addition to a high-performance embedded MPC8xx core, the MPC850 integrates system functions, such as a versatile memory controller and a communications processor module (CPM) that incorporates a specialized, independent RISC communications processor (referred to as the CP). This separate processor off-loads peripheral tasks from the embedded MPC8xx core.