MPC8360E

• e300 PowerPC processor core (enhanced version of the MPC603e core)
- Operates at up to 400 MHz (for the MPC8358E)
- High-performance, superscalar processor core
- Floating-point, integer, load/store, system register, and branch processing units
- 32-Kbyte instruction cache, 32-Kbyte data cache
- Lockable portion of L1 cache
- Dynamic power management
- Software-compatible with the Freescale processor families implementing the Power Architecture™ technology
• QUICC Engine unit
- Two 32-bit RISC controllers for flexible support of the communications peripherals, each operating up to 400 MHz (for the MPC8358E)
- Serial DMA channel for receive and transmit on all serial channels
- QE peripheral request interface (for SEC, PCI, IEEE® Std 1588™)
- Six UCCs on the MPC8358E supporting the following protocols and interfaces (not all of them simultaneously):
IEEE Std. 1588 protocol supported
10/100 Mbps Ethernet/IEEE Std. 802.3® CDMA/CS interface through a media-independent interface (MII, RMII, RGMII)1
1000 Mbps Ethernet/IEEE Std. 802.3 CDMA/CS interface through a media-independent interface (GMII, RGMII, TBI, RTBI) on UCC1 and UCC2
9.6K jumbo frames
ATM full-duplex SAR, up to 622 Mbps (OC-12/STM-4), AAL0, AAL1 and AAL5 in accordance ITU-T I.363.5
ATM AAL2 CPS, SSSAR, and SSTED up to 155 Mbps (OC-3/STM-1) Mbps full duplex (with 4 CPS packets per cell) in accordance ITU-T I.366.1 and I.363.2
ATM traffic shaping for CBR, VBR, UBR, and GFR traffic types compatible with ATM forum TM4.1 for up to 64K simultaneous ATM channels
ATM AAL1 structured and unstructured circuit emulation service (CES 2.0) in accordance with ITU-T I.163.1 and ATM Forum af-vtoa-00-0078.000
IMA (Inverse Multiplexing over ATM) for up to 31 IMA links over 8 IMA groups in accordance with the ATM forum AF-PHY-0086.000 (Version 1.0) and AF-PHY-0086.001 (Version 1.1)
ATM Transmission Convergence layer support in accordance with ITU-T I.432
ATM OAM handling features compatible with ITU-T I.610
PPP, Multi-Link (ML-PPP), Multi-Class (MC-PPP) and PPP mux in accordance with theVfollowing RFCs: 1661, 1662, 1990, 2686 and 3153
IP support for IPv4 packets including TOS, TTL and header checksum processing
Ethernet over first mile IEEE Std. 802.3ah®
Shim header
Ethernet-to-Ethernet/AAL5/AAL2 inter-working
L2 Ethernet switching using MAC address or IEEE Std. 802.1P/Q® VLAN tags
ATM (AAL2/AAL5) to Ethernet (IP) interworking in accordance with RFC2684 including bridging of ATM ports to Ethernet ports
Extensive support for ATM statistics and Ethernet RMON/MIB statistics
AAL2 protocol rate up to 4 CPS at OC-3/STM-1 rate
Packet over Sonet (POS) up to 622-Mbps full-duplex 124 MultiPHY
POS hardware; microcode must be loaded as an IRAM package
Transparent up to 70-Mbps full-duplex
HDLC up to 70-Mbps full-duplex
HDLC BUS up to 10 Mbps
Asynchronous HDLC
UART
BISYNC up to 2 Mbps
User-programmable Virtual FIFO size
QUICC Multichannel Controller (QMC) for 64 TDM channels
- One UTOPIA/POS interface on the MPC8358E supporting 31/124 MultiPHY
- Two serial peripheral interfaces (SPI); SPI2 is dedicated to Ethernet PHY management
- Four TDM interfaces on the MPC8358E with 1-bit mode for E3/T3 rates in clear channel
- Sixteen independent baud rate generators and 30 input clock pins for supplying clocks to UCC serial channels
- Four independent 16-bit timers that can be interconnected as four 32-bit timers
- Interworking functionality:
Layer 2 10/100-Base T Ethernet switch
ATM-to-ATM switching (AAL0, 2, 5)
Ethernet-to-ATM switching with L3/L4 support
PPP interworking
• Security engine is optimized to handle all the algorithms associated with IPSec, SSL/TLS, SRTP,802.11i, iSCSI, and IKE processing. The security engine contains four crypto-channels, a controller, and a set of crypto execution units (EUs).
- Public key execution unit (PKEU) supporting the following:
RSA and Diffie-Hellman
Programmable field size up to 2048 bits
Elliptic curve cryptography
F2m and F(p) modes
Programmable field size up to 511 bits
- Data encryption standard execution unit (DEU)
DES, 3DES
Two key (K1, K2) or three key (K1, K2, K3)
ECB and CBC modes for both DES and 3DES
- Advanced encryption standard unit (AESU)
- Implements the Rinjdael symmetric key cipher
- Key lengths of 128, 192, and 256 bits, two key
ECB, CBC, CCM, and counter modes
- ARC four execution unit (AFEU)
Implements a stream cipher compatible with the RC4 algorithm
40- to 128-bit programmable key
- Message digest execution unit (MDEU)
SHA with 160-, 224-, or 256-bit message digest
MD5 with 128-bit message digest
HMAC with either SHA or MD5 algorithm
- Random number generator (RNG)
- Four crypto-channels, each supporting multi-command descriptor chains
Static and/or dynamic assignment of crypto-execution units via an integrated controller
Buffer size of 256 bytes for each execution unit, with flow control for large data sizes
- Storage/NAS XOR parity generation accelerator for RAID applications
• DDR SDRAM memory controller on the MPC8358E
- Programmable timing supporting both DDR1 and DDR2 SDRAM
- On the MPC8358E, the DDR bus can be configured as a 32-bit or a 64-bit bus
- 32- or 64-bit data interface, up to 266 MHz (for the MPC8358E) data rate
- Four banks of memory, each up to 1 Gbyte
- DRAM chip configurations from 64 Mbits to 1 Gigabit with x8/x16 data ports
- Full ECC support
- Page mode support (up to 16 simultaneous open pages for DDR1, up to 32 simultaneous open pages for DDR2)
- Contiguous or discontiguous memory mapping
- Read-modify-write support
- Sleep mode support for self refresh SDRAM
- Supports auto refreshing
- Supports source clock mode
- On-the-fly power management using CKE
- Registered DIMM support
- 2.5-V SSTL2 compatible I/O for DDR1, 1.8-V SSTL2 compatible I/O for DDR2
- External driver impedance calibration
- On-die termination (ODT)
• PCI interface
- PCI Specification Revision 2.3 compatible
- Data bus widths:
Single 32-bit data PCI interface that operates at up to 66 MHz
- PCI 3.3-V compatible (not 5-V compatible)
- PCI host bridge capabilities on both interfaces
- PCI agent mode supported on PCI interface
- Support for PCI-to-memory and memory-to-PCI streaming
- Memory prefetching of PCI read accesses and support for delayed read transactions
- Support for posting of processor-to-PCI and PCI-to-memory writes
- On-chip arbitration, supporting five masters on PCI
- Support for accesses to all PCI address spaces
- Parity support
- Selectable hardware-enforced coherency
- Address translation units for address mapping between host and peripheral
- Dual address cycle supported when the device is the target
- Internal configuration registers accessible from PCI
• Local bus controller (LBC)
- Multiplexed 32-bit address and data operating at up to 133 MHz
- Eight chip selects support eight external slaves
- Up to eight-beat burst transfers
- 32-, 16-, and 8-bit port sizes are controlled by an on-chip memory controller
- Three protocol engines available on a per chip select basis:
General-purpose chip select machine (GPCM)
Three user programmable machines (UPMs)
Dedicated single data rate SDRAM controller
- Parity support
- Default boot ROM chip select with configurable bus width (8-, 16-, or 32-bit)
• Programmable interrupt controller (PIC)
- Functional and programming compatibility with the MPC8260 interrupt controller
- Support for 8 external and 35 internal discrete interrupt sources
- Support for one external (optional) and seven internal machine checkstop interrupt sources
- Programmable highest priority request
- Four groups of interrupts with programmable priority
- External and internal interrupts directed to communication processor
- Redirects interrupts to external INTA pin when in core disable mode
- Unique vector number for each interrupt source
• Dual industry-standard I²C interfaces
- Two-wire interface
- Multiple master support
- Master or slave I2C mode support
- On-chip digital filtering rejects spikes on the bus
- System initialization data is optionally loaded from I2C-1 EPROM by boot sequencer embedded hardware
• DMA controller
- Four independent virtual channels
- Concurrent execution across multiple channels with programmable bandwidth control
- All channels accessible by local core and remote PCI masters
- Misaligned transfer capability
- Data chaining and direct mode
- Interrupt on completed segment and chain
- DMA external handshake signals: DMA_DREQ[0:3]/DMA_DACK[0:3]/DMA_DONE[0:3].There is one set for each DMA channel. The pins are multiplexed to the parallel IO pins with other QE functions.
• DUART
- Two 4-wire interfaces (RxD, TxD, RTS, CTS)
- Programming model compatible with the original 16450 UART and the PC16550D
• System timers
- Periodic interrupt timer
- Real-time clock
- Software watchdog timer
- Eight general-purpose timers
• IEEE Std. 1149.1™ compliant, JTAG boundary scan
• Integrated PCI bus and SDRAM clock generation

Notes:
1. Functional and tested operating conditions are given in Table 2. Absolute maximum ratings are stress ratings only, and functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause permanent damage to the device.
2. Caution: MVIN must not exceed GVDD by more than 0.3 V. This limit may be exceeded for a maximum of 100 ms during power-on reset and power-down sequences.
3. Caution: OVIN must not exceed OVDD by more than 0.3 V. This limit may be exceeded for a maximum of 100 ms during power-on reset and power-down sequences.
4. Caution: LVIN must not exceed LVDD by more than 0.3 V. This limit may be exceeded for a maximum of 100 ms during power-on reset and power-down sequences.
5. (M,L,O)VIN and MVREF may overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 3.
6. OVIN on the PCI interface may overshoot/undershoot according to the PCI Electrical Specification for 3.3-V operation,as shown in Figure 4.