Features: • Branch processing unit
- Four instructions fetched per clock
- One branch processed per cycle (plus resolving two speculations)
- Up to one speculative stream in execution, one additional speculative stream in fetch
- 512-entry branch history table (BHT) for dynamic prediction
- 64-entry, four-way set-associative branch target instruction cache (BTIC) for eliminating branch delay slots
• Dispatch unit
- Full hardware detection of dependencies (resolved in the execution units)
- Dispatch two instructions to six independent units (system, branch, load/store, fixed-point unit 1, fixed-point unit 2, floating-point)
- Serialization control (predispatch, postdispatch, execution serialization)
• Decode
- Register file access
- Forwarding control
- Partial instruction decode
• Completion
- Six-entry completion buffer
- Instruction tracking and peak completion of two instructions per cycle
- Completion of instructions in program order while supporting out-of-order instruction execution, completion serialization, and all instruction flow changes
• Fixed point units (FXUs) that share 32 GPRs for integer operands
- Fixed Point Unit 1 (FXU1) -multiply, divide, shift, rotate, arithmetic, logical
- Fixed Point Unit 2 (FXU2) -shift, rotate, arithmetic, logical
- Single-cycle arithmetic, shifts, rotates, logical
- Multiply and divide support (multi-cycle)
- Early out multiply
• Floating-point unit and a 32-entry FPR file
- Support for IEEE standard 754 single- and double-precision floating-point arithmetic
- Hardware support for divide
- Hardware support for denormalized numbers
- Single-entry reservation station
- Supports non-IEEE mode for time-critical operations
- Three-cycle latency, one-cycle throughput, single-precision multiply-add
- Three-cycle latency, one-cycle throughput, double-precision add
Specifications
|
Characteristic |
Symbol |
Maximum Value |
Unit |
Notes |
|
Core supply voltage
PLL supply voltage
L2 DLL supply voltage
Processor bus supply voltage
L2 bus supply voltage |
VDD
AVDD
L2AVDD
OVDD
L2OVDD
Vin
Vin
Vin
Tstg |
- 0.3 to 2.5
- 0.3 to 2.5
- 0.3 to 2.5
- 0.3 to 3.6
- 0.3 to 3.6
- 0.3 to OVDD + 0.3 V
- 0.3 to L2OVDD + 0.3 V
- 0.3 to 3.6
- 55 to 150 |
V
V
V
V
V
V
V
V
|
4
4
4
3
3
2, 5
2, 5
|
|
Input voltage |
Processor bus
L2 bus
JTAG signals |
|
Storage temperature range |
Notes:
1. Functional and tested operating conditions are given in Table 3. Absolute maximum ratings are stress ratings only, and functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause permanent damage to the device.
2. Caution: Vin must not exceed OVDD or L2OVDD by more than 0.3 V at any time including during power-on reset.
3. Caution: L2OVDD/OVDD must not exceed VDD/AVDD/L2AVDD by more than 1.6 V during normal operation. During power-on reset and power-down sequences, L2OVDD/OVDD may exceed VDD/AVDD/L2AVDD by up to 3.3 V for up to 20 ms, or by 2.5 V for up to 40 ms. Excursions beyond 3.3 V or 40 ms are not supported.
4. Caution: VDD/AVDD/L2AVDD must not exceed L2OVDD/OVDD by more than 0.4 V during normal operation. During power-on reset and power-down sequences, VDD/AVDD/L2AVDD may exceed L2OVDD/OVDD by up to 1.0 V for up to 20 ms, or by 0.7 V for up to 40 ms. Excursions beyond 1.0 V or 40 ms are not supported.
5. This is a DC specifications only. Vin may overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 2.
MPC755 Data Sheet
