MPC7400

•Branch processing unit
-Four instructions fetched per clock
-One branch processed per cycle (plus resolving 2 speculations)
-Up to 1 speculative stream in execution, 1 additional speculative stream in fetch
-512-entry branch history table (BHT) for dynamic prediction
-64-entry, 4-way set associative Branch Target Instruction Cache (BTIC) for eliminating branch
delay slots
•Dispatch unit
-Full hardware detection of dependencies (resolved in the execution units)
•Dispatch two instructions to eight independent units (system, branch, load/store, fixed-point
unit 1, fixed-point unit 2, floating-point, AltiVec permute, AltiVec ALU)
-Serialization control (predispatch, postdispatch, execution serialization)
-Decode
-Register file access
-Forwarding control
-Partial instruction decode
•Completion
-8 entry completion buffer
-Instruction tracking and peak completion of two instructions per cycle
-Completion of instructions in program order while supporting out-of-order instruction
execution, completion serialization and all instruction flow changes
•Fixed-point units (FXUs) that share 32 GPRs for integer operands
•Fixed-point unit 1 (FXU1)ultiply, divide, shift, rotate, arithmetic, logical
-Fixed-point unit 2 (FXU2)hift, rotate, arithmetic, logical
-Single-cycle arithmetic, shifts, rotates, logical
-Multiply and divide support (multi-cycle)
-Early out multiply
•Three-stage floating-point unit and a 32-entry FPR file
-Support for IEEE-754 standard single and double-precision floating-point arithmetic
-3 cycle latency, 1 cycle throughput (single or double precision)
-Hardware support for divide
-Hardware support for denormalized numbers
-Time deterministic non-IEEE mode

• System unit
- Executes CR logical instructions and miscellaneous system instructions
- Special register transfer instructions