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MPC7451

Features: • High-performance, superscalar microprocessor• Eleven independent execution units and three register files• Three issue queues FIQ, VIQ, and GIQ can accept as many as one, two, and three instructions, respectively, in a cycle. Instruction dispatch requires the followin...

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MPC7451: Features: • High-performance, superscalar microprocessor• Eleven independent execution units and three register files• Three issue queues FIQ, VIQ, and GIQ can accept as many as on...

MPC7451 Data Sheet

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Part Number:
MPC7451
Supply Ability:
5000

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  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

• High-performance, superscalar microprocessor
• Eleven independent execution units and three register files
• Three issue queues FIQ, VIQ, and GIQ can accept as many as one, two, and three instructions, respectively, in a cycle. Instruction dispatch requires the following:
• Rename buffers
• Dispatch unit
• Completion unit
• Separate on-chip L1 instruction and data caches (Harvard architecture)
• Level 2 (L2) cache interface
• Level 3 (L3) cache interface
• Separate memory management units (MMUs) for instructions and data
• Efficient data flow
• Multiprocessing support features include the following:
• Power and thermal management
• Performance monitor can be used to help debug system designs and improve software efficiency.
• In-system testability and debugging features through JTAG boundary-scan capability
• Testability
• Reliability and serviceability


Specifications

Characteristic Symbol Maximum Value Unit Notes
Core supply voltage VDD 0.3 to 1.95 V 4
PLL supply voltage AVDD 0.3 to 1.95 V 4
Processor bus supply voltage BVSEL = 0 OVDD 0.3 to 1.95 V 3, 6
BVSEL = HRESET or OVDD OVDD 0.3 to 2.7 V 3, 7
L3 bus supply voltage L3VSEL = ¬HRESET GVDD 0.3 to 1.65 V 3, 8
L3VSEL = 0 GVDD 0.3 to 1.95 V 3, 9
L3VSEL = HRESET or GVDD GVDD 0.3 to 2.7 V 3, 10
Input voltage Processor bus Vin 0.3 to OVDD + 0.3 V 2, 5
L3 bus Vin 0.3 to GVDD + 0.3 V 2, 5
JTAG signals Vin 0.3 to OVDD + 0.3 V  
Storage temperature range Tstg 55 to 150 °C  



Description

The MPC7451 is the third implementation of the fourth generation (G4) microprocessors from Motorola. It implements the full PowerPC 32-bit architecture and is targeted at networking and computing systems applications. The MPC7451 consists of a processor core, a 256-Kbyte L2, and an internal L3 tag and controller which support a glueless backside L3 cache through a dedicated high bandwidth interface.

Figure 1 shows a block diagram of the MPC7451. The core is a high-performance superscalar design supporting a double-precision floating-point unit and a SIMD multimedia unit. The memory storage subsystem supports the MPX bus interface to main memory and other system resources. The L3 interface supports 1 or 2 Mbytes of external SRAM for L3 cache data.

Note that the MPC7451 is a footprint-compatible, drop-in replacement in a MPC7450 application as long as the core power supply is 1.6 V.




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