Features: • High-performance, superscalar microprocessor
- As many as 4 instructions can be fetched from the instruction cache at a time
- As many as 3 instructions can be dispatched to the issue queues at a time
- As many as 12 instructions can be in the instruction queue (IQ)
- As many as 16 instructions can be at some stage of execution simultaneously
- Single-cycle execution for most instructions
- One instruction per clock cycle throughput for most instructions
- Seven-stage pipeline control
• Eleven independent execution units and three register files
- Branch processing unit (BPU) features static and dynamic branch prediction
128-entry (32-set, four-way set-associative) branch target instruction cache (BTIC), a cache of branch instructions that have been encountered in branch/loop code sequences. If a target instruction is in the BTIC, it is fetched into the instruction queue a cycle sooner than it can be made available from the instruction cache. Typically, a fetch that hits the BTIC provides the first four instructions in the target stream.
2048-entry branch history table (BHT) with two bits per entry for four levels of prediction - not-taken, strongly not-taken, taken, strongly taken
Up to three outstanding speculative branches
Branch instructions that do not update the count register (CTR) or link register (LR) are often removed from the instruction stream.
8-entry link register stack to predict the target address of Branch Conditional to Link Register ( bclr ) instructions.
- Four integer units (IUs) that share 32 GPRs for integer operands
Three identical IUs (IU1a, IU1b, and IU1c) can execute all integer instructions except multiply, divide, and move to/from special-purpose register instructions.
IU2 executes miscellaneous instructions including the CR logical operations, integer multiplication and division instructions, and move to/from special-purpose register instructions.
- Five-stage FPU and a 32-entry FPR file
Fully IEEE 754-1985-compliant FPU for both single- and double-precision operations
Supports non-IEEE mode for time-critical operations
Hardware support for denormalized numbers
Thirty-two 64-bit FPRs for single- or double-precision operands
- Four vector units and 32-entry vector register file (VRs)
Vector permute unit (VPU) ARCHIVED BY FREESCALE SEMICONDUCTOR, INC.
Specifications
|
Characteristic |
Symbol |
Maximum Value |
Unit |
Notes |
|
Core supply voltage
PLL supply voltage |
VDD
AVDD
OVDD
OVDD
GVDD
GVDD
GVDD
Vin
Vin
Vin
Tstg |
0.3 to 1.95
0.3 to 1.95
0.3 to 1.95
0.3 to 2.7
0.3 to 1.65
0.3 to 1.95
0.3 to 2.7
0.3 to OVDD + 0.3
0.3 to GVDD + 0.3
0.3 to OVDD + 0.3
55 to 150 |
V
V
V
V
V
V
V
V
V
V
|
4
4
3, 6
3, 7
3, 8
3, 9
3, 10
2, 5
2, 5
|
|
Processor bus supply voltage |
BVSEL = 0
BVSEL = HRESET or OVDD
L3VSEL = ¬HRESET
L3VSEL = 0
L3VSEL = HRESET or GVDD
Processor bus
L3 bus
JTAG signals |
|
L3 bus supply voltage |
|
Input voltage |
|
Storage temperature range |
Notes :
1. Functional and tested operating conditions are given in Table 4. Absolute maximum ratings are stress ratings only, and functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause permanent damage to the device.
2. Caution : Vin must not exceed OVDD or GVDD
by more than 0.3 V at any time including during power-on reset.
3. Caution : OVDD/GVDD must not exceed VDD/AVDD by more than 2.0 V at any time including during power-on reset.
4. Caution : VDD/AVDD must not exceed OVDD/GVDD by more than 0.4 V at any time including during power-on reset.
5. Vin may overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 2.
6. BVSEL must be set to 0, such that the bus is in 1.8 V mode.
7. BVSEL must be set to HRESET or 1, such that the bus is in 2.5 V mode.
8. L3VSEL must be set to ¬HRESET (inverse of HRESET), such that the bus is in 1.5 V mode.
9. L3VSEL must be set to 0, such that the bus is in 1.8 V mode.
10. L3VSEL must be set to HRESET or 1, such that the bus is in 2.5 V mode. ARCHIVED BY FREESCALE
MPC7450 Data Sheet
