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MPC7448

Features: This section summarizes features of the MPC7448 implementation of the PowerPC architecture.Major features of the MPC7448 are as follows:• High-performance, superscalar microprocessor - Up to four instructions can be fetched from the instruction cache at a time. - Up to three instru...

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MPC7448: Features: This section summarizes features of the MPC7448 implementation of the PowerPC architecture.Major features of the MPC7448 are as follows:• High-performance, superscalar microprocessor...

MPC7448 Data Sheet

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Part Number:
MPC7448
Supply Ability:
5000

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Description



Features:

This section summarizes features of the MPC7448 implementation of the PowerPC architecture.
Major features of the MPC7448 are as follows:
• High-performance, superscalar microprocessor
  - Up to four instructions can be fetched from the instruction cache at a time.
  - Up to three instructions plus a branch instruction can be dispatched to the issue queues at a time.
  - Up to 12 instructions can be in the instruction queue (IQ).
  - Up to 16 instructions can be at some stage of execution simultaneously.
  - Single-cycle execution for most instructions
  - One instruction per clock cycle throughput for most instructions
  - Seven-stage pipeline control
• Eleven independent execution units and three register files
  - Branch processing unit (BPU) features static and dynamic branch prediction
  128-entry (32-set, four-way set-associative) branch target instruction cache (BTIC), a cache
    of branch instructions that have been encountered in branch/loop code sequences. If a target
    instruction is in the BTIC, it is fetched into the instruction queue a cycle sooner than it can
    be made available from the instruction cache. Typically, a fetch that hits the BTIC provides
    the first four instructions in the target stream.
  2048-entry branch history table (BHT) with 2 bits per entry for four levels of
    prediction-not taken, strongly not taken, taken, and strongly taken
  Up to three outstanding speculative branches
  Branch instructions that do not update the count register (CTR) or link register (LR) are
    often removed from the instruction stream.
  Eight-entry link register stack to predict the target address of Branch Conditional to Link
    Register (bclr) instructions
  - Four integer units (IUs) that share 32 GPRs for integer operands
  Three identical IUs (IU1a, IU1b, and IU1c) can execute all integer instructions except
     multiply, divide, and move to/from special-purpose register instructions.
  IU2 executes miscellaneous instructions, including the CR logical operations, integer
    multiplication and division instructions, and move to/from special-purpose register instructions.
  - Five-stage FPU and 32-entry FPR file
  Fully IEEE 754-1985compliant FPU for both single- and double-precision operations
  Supports non-IEEE mode for time-critical operations
  Hardware support for denormalized numbers
  Thirty-two 64-bit FPRs for single- or double-precision operands


Specifications

Characteristic Symbol Maximum Value Unit Notes
Core supply voltage VDD 0.3 to 1.4 V 2
PLL supply voltage AVDD 0.3 to 1.4 V 2
Processor bus supply voltage I/O Voltage Mode = 1.5 V OVDD 0.3 to 1.8 V 3
I/O Voltage Mode = 1.8 V 0.3 to 2.2 3
I/O Voltage Mode = 2.5 V 0.3 to 3.0 3
Input voltage Processor bus Vin 0.3 to OVDD + 0.3 V 4
JTAG signals Vin 0.3 to OVDD + 0.3 V  
Storage temperature range Tstg 55 to 150 °C  

Notes:
1. Functional and tested operating conditions are given in Table 4. Absolute maximum ratings are stress ratings only and functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause permanent damage to the device.
2. See Section 9.2, "Power Supply Design and Sequencing" for power sequencing requirements.
3. Bus must be configured in the corresponding I/O voltage mode; see Table 3.
4. Caution: Vin must not exceed OVDD by more than 0.3 V at any time including during power-on reset except as allowed by the overshoot specifications. Vin may overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 2.




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