MPC2605

Features: • Single Chip L2 Cache for PowerPC • 66 MHz Zero Wait State Performance (2111 Burst) • FourWay Set Associative Cache Design • 32K x 72 Data Memory Array • 8K x 18 Tag Array • Address Parity Support • LRU Cache Control Logic • CopyBack or Wr...

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SeekIC No. : 004426028 Detail

MPC2605: Features: • Single Chip L2 Cache for PowerPC • 66 MHz Zero Wait State Performance (2111 Burst) • FourWay Set Associative Cache Design • 32K x 72 Data Memory Array • 8K ...

floor Price/Ceiling Price

Part Number:
MPC2605
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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268 Transactions

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evaluate  (4.8 stars)

Upload time: 2024/11/26

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Product Details

Description



Features:

• Single Chip L2 Cache for PowerPC
• 66 MHz Zero Wait State Performance (2111 Burst)
• FourWay Set Associative Cache Design
• 32K x 72 Data Memory Array
• 8K x 18 Tag Array
• Address Parity Support
• LRU Cache Control Logic
• CopyBack or WriteThrough Modes of Operation
• CopyBack Buffer for Improved Performance
• Single 3.3 V Power Supply
• 5 V Tolerant I/O
• One, Two, or Four Chip Cache Solution (256KB, 512KB, or 1MB)
• Single Clock Operation
• Compliant with IEEE Standard 1149.1 Test Access Port (JTAG)
• Supports up to Four Processors in a Shared Cache Configuration
• High Board Density 25 mm 241 PBGA Package



Pinout

  Connection Diagram


Specifications

Rating
Symbol
Value
Unit
Power Supply Voltage
VDD
0.5 to + 4.6
V
Voltage Relative to VSS
Vin, Vout
0.5 to VDD + 0.5
V
Output Current (per I/O)
Iout
± 20
mA
Power Dissipation (Note 2)
PD
-
W
Temperature Under Bias
Tbias
10 to + 85
Operating Temperature
TJ
0 to + 125
Storage Temperature
Tstg
55 to + 125



Description

The MPC2605 is a single chip, 256KB integrated lookaside cache with copyback capability designed for PowerPC applications (MPC603 and MPC604). Using 0.38 mm technology along with standard cell logic technology, the MPC2605 integrates data, tag, host interface, and least recently used (LRU) memory with a cache controller to provide a 256KB, 512KB, or 1 MB Level 2 cache with one, two, or four chips on a 64bit PowerPC bus.




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