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MPC2002

Features: • PowerPCstyle Burst Counter on Board• Dual Readout SIMM for Circuit Density• Single 5 V ± 5% Power Supply• All Inputs and Outputs are TTL Compatible• Three State Outputs• Byte Parity• Byte Write Capability• Fast Module Clock Rates: 66 MHz,...

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SeekIC No. : 004426012 Detail

MPC2002: Features: • PowerPCstyle Burst Counter on Board• Dual Readout SIMM for Circuit Density• Single 5 V ± 5% Power Supply• All Inputs and Outputs are TTL Compatible• Three S...

MPC2002 Data Sheet

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Part Number:
MPC2002
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/11/26

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Product Details

Description



Features:

• PowerPCstyle Burst Counter on Board
• Dual Readout SIMM for Circuit Density
• Single 5 V ± 5% Power Supply
• All Inputs and Outputs are TTL Compatible
• Three State Outputs
• Byte Parity
• Byte Write Capability
• Fast Module Clock Rates: 66 MHz, 60 MHz, 50MHz
• Decoupling Capacitors for each Fast Static RAM
• High Quality MultiLayer FR4 PWB With Separate Power and Ground Planes
• I/Os are 3.3 V Compatible


Pinout

Connection Diagram


Specifications

Rating
Symbol
Value
Unit
Power Supply Voltage
VCC
0.5 to + 7.0
V
Voltage Relative to VSS for Any
Pin Except VCC
Vin, Vout
0.5 to VCC + 0.5
V
Output Current (per I/O)
Iout
± 30
mA
Power Dissipation
PD
± 30
W
Temperature Under Bias
Tbias
10 to + 85
Operating Temperature
TA
0 to +70
Storage Temperature
Tstg
55 to + 125



Description

The MPC2002SG and MPC2003SG are designed to provide a burstable, high performance, 256K/512K L2 cache for the PowerPC 60x processors. The MPC2002SG and MPC2003SG are configured as 32K x 72 and 64K x 72 bits in a 136 pin dual readout single inline memory module (DIMM). The module uses four of Motorola's MCM67M518 or MCM67M618 BiCMOS BurstRAMs.

MPC2002SG and MPC2003SG can be initiated with either transfer start processor (TSP) or transfer start controller (TSC). Subsequent burst addresses are generated internal to the BurstRAM by the burst address advance (BAA) pin. Write cycles of MPC2002SG and MPC2003SG are internally self timed and are initiated by the rising edge of the clock (K) input. Eight write enables are provided for byte write control.

The MPC2002SG and MPC2003SG family is designed to interface with the PowerPC 60x bus and requires external tag. PD0 PD2 are reserved for density and speed identification.




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