MPC2105B

Features: • PowerPCstyle Burst Counter on Chip• FlowThrough Data I/O• Plug and Pin Compatibility• Multiple Clock Pins for Reduced Loading• 20 W Series Resistors on DL and DH Pins for Noise Reduction (MPC2105A/6A)• All Cache Data and Tag I/Os are LVTTL (3.3 V) Co...

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SeekIC No. : 004426020 Detail

MPC2105B: Features: • PowerPCstyle Burst Counter on Chip• FlowThrough Data I/O• Plug and Pin Compatibility• Multiple Clock Pins for Reduced Loading• 20 W Series Resistors on DL a...

floor Price/Ceiling Price

Part Number:
MPC2105B
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/11/26

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Product Details

Description



Features:

• PowerPCstyle Burst Counter on Chip
• FlowThrough Data I/O
• Plug and Pin Compatibility
• Multiple Clock Pins for Reduced Loading
• 20 W Series Resistors on DL and DH Pins for Noise Reduction (MPC2105A/6A)
• All Cache Data and Tag I/Os are LVTTL (3.3 V) Compatible
• Three State Outputs
• Byte Write Capability
• Fast Module Clock Rates: Up to 66 MHz
• Fast SRAM Access Times: 10 ns for Tag RAM Match 9 ns for Data RAM
• Decoupling Capacitors for Each Fast Static RAM
• High Quality MultiLayer FR4 PWB With Separate Power and Ground Planes
• 178 Pin Card Edge Module
• Burndy Connector, Part Number: ELF178KSC3Z50



Specifications

Rating
Symbol
Value
Unit
Power Supply Voltage
VCC
0.5 to + 7.0
V
Voltage Relative to VSS
Vin, Vout
0.5 to VCC + 0.5
V
Output Current (per I/O) Data RAM
Tag
Iout
± 30
± 20
mA
Power Dissipation MPC2105A/B
MPC2106A/B
PD
4.6
9.2
W
Temperature Under Bias
Tbias
10 to + 85
Operating Temperature
TA
0 to +70
Storage Temperature
Tstg
55 to + 125


NOTE:
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability.
This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this highimpedance circuit.
This BiCMOS memory circuit has been designed to meet the dc and ac specifications
shown in the tables, after thermal equilibrium has been established.
This device contains circuitry that will ensure the output devices are in HighZ at power up.




Description

The MPC2105A/B and the MPC2106A/B are designed to provide burstable, high performance L2 cache for the PowerPC 60x microprocessor family in conformance with the PowerPC Reference Platform (PReP) and the PowerPC Common Hardware Reference Platform (CHRP) specifications.

The MPC2105A/B and MPC2106A/B utilize synchronous BurstRAMs. The modules are configured as 64K x 72, and 128K x 72 bits in a 178 (89 x 2) pin DIMM format. The MPC2105A/B uses four of the 3 V 64K x 18; the MPC2106A/B uses eight of the 3 V 64K x 18. For tag bits, a 5 V cache tag RAM configured as 16K x 12 for tag field plus 16K x 2 for valid and dirty status bits is used.

Bursts of MPC2105A/B and the MPC2106A/B can be initiated with the ADS signal. Subsequent burst addresses are generated internal to the BurstRAM by the CNTEN signal. Write cycles are internally self timed and are initiated by the rising edge of the clock (CLKx) inputs. Eight write enables are provided for byte write control. Presence detect pins are available for auto configuration of the cache control.

The MPC2105A/B and the MPC2106A/B family pinout will support 5 V and 3.3 V components for a clear path to lower voltage and power savings. Both power supplies must be connected. All of these cache modules are plug and pin compatible with each other.




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