MPC2104P

NOTE:
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are eceeded. Functional operation should be restricted to RECOMMENDED OPERATING ONDITIONS. Exposure to higher than recommended voltages for xtended periods of time could affect device reliability.

The MPC2104P (256KB) and MPC2105P (512KB) are designed to provide urstable, high performance L2 cache for the PowerPC 60x microprocessor family n conformance with the PowerPC Reference Platform (PReP) and the PowerPC ommon Hardware Reference Platform (CHRP) specifications.

The c utilize synchronous BurstRAMs. The MPC2104P odule is configured as 32K x 64 bits and uses two of the 3.3 V 32K x 32 data RAMs. he MPC2105P is configured as 64K x 64 bits and uses two of the 3.3 V 64K x 32 ata RAMs. Both modules are in a 178 (89 x 2) pin DIMM format. For tag bits on the 104P, a 5 V cache tag RAM configured as 8K x 14 for tag field plus 8K x 2 for valid nd dirty status bits is used. For tag bits on the 2105P, a 5 V cache tag RAM

configured as 16K x 14 for tag field plus 16K x 2 for valid and dirty status bits is used. Bursts of MPC2104P and MPC2105P can be initiated with the ADS signal. Subsequent burst addresses are enerated internally to the BurstRAM by the CNTEN signal.

Write cycles of MPC2104P and MPC2105P are internally selftimed and are initiated by the rising edge of the clock CLKx) inputs. Writes are global with two inputs for reduced loading. resence detect pins are available for auto configuration of the cache control.

The MPC2104P and MPC2105P family pinout will support 5 V and 3.3 V components for a clear path o lower voltage and power savings. Both power supplies must be connected. ll of these cache modules are plug and pin compatible with each other.