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ML67Q4050

Features: • CPU - 32-bit RISC CPU (ARM7TDMI) - Little endian byte order - Maximum operating frequency: 33.333 MHz - Instruction set: Free switching between a highly dense 32-bit instruction set and a 16-bit subset offering higher object code efficiency - General-purpose registers: 32-bit * 3...

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SeekIC No. : 004422220 Detail

ML67Q4050: Features: • CPU - 32-bit RISC CPU (ARM7TDMI) - Little endian byte order - Maximum operating frequency: 33.333 MHz - Instruction set: Free switching between a highly dense 32-bit instruction se...

ML67Q4050 Data Sheet

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Part Number:
ML67Q4050
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/11/26

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Product Details

Description



Features:

• CPU
   - 32-bit RISC CPU (ARM7TDMI)
   - Little endian byte order
   - Maximum operating frequency: 33.333 MHz
   - Instruction set: Free switching between a highly dense 32-bit instruction set and a 16-bit subset offering
   higher object code efficiency
   - General-purpose registers: 32-bit * 31
   - Barrel shifter: Simultaneous ALU and barrel shift operations in the same instruction
   - Multiplier (32-bit * 8-bit)
   - JTAG interface for debugging
• Built-in Memory
   - SRAM: 16Kbytes (4K * 32bits), 1-cycle access, connected to the processor bus
   - Built-in Flash ROM: 128Kbytes (ML67Q4051, ML67Q4061) or 64Kbytes (ML67Q4050, ML67Q4060),
   1-cycle access, connected to the processor bus
   FlashROM programming cycle count: 100 (max.)
   - BootROM: 8Kbytes, connected to AHB
• External Memory Controller (only for ML67Q4050 series)
   - Programmable access timing setting for each space
   - ROM (Flash) access function
   - Supports 1 bank * 16Mbytes ROM space.
   - Supports 16-bit and 32-bit devices
   - Supports flash memories
   - Supports page accessing
   - SRAM access function
   - Supports 1 bank * 16Mbytes SRAM space.
   - Supports 16-bit and 32-bit devices.
   - Supports asynchronous SRAM.
   - External I/O access function
   - Supports 2-bank / space.
   - Supports 8-bit, 16-bit, and 32-bit devices.
   - Supports asynchronous wait from external devices.
   - Allows address setup in units of single cycles, RE/WE pulse, and data-off timing setting.
• Interrupt Controller
   - One fast interrupt (FIQ) source (external)
   - 31 interrupt (IRQ) sources (40 interrupt sources for ML67Q4050 series)
   - Independent masking for each FIQ and IRQ source
   - Independent interrupt priority level settings for each IRQ source
   - Priority control blocking IRQ requests with priority levels at or below those for interrupt requests
   currently being processed


Pinout

Connection Diagram


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