ML6691*

Features: Conforms to the Fast Ethernet 100BASE-TIEEE 802.3m standardIntegrated 4B/5B encoder/decoderIntegrated Stream Cipher scrambler/descramblerCompliant MII interfaceTwo-wire serial interface management port forconfiguration and controlOn-chip 25 MHz crystal oscillatorInterfaces to either AMD'...

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ML6691* Picture
SeekIC No. : 004422205 Detail

ML6691*: Features: Conforms to the Fast Ethernet 100BASE-TIEEE 802.3m standardIntegrated 4B/5B encoder/decoderIntegrated Stream Cipher scrambler/descramblerCompliant MII interfaceTwo-wire serial interface ma...

floor Price/Ceiling Price

Part Number:
ML6691*
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/11/26

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Product Details

Description



Features:

Conforms to the Fast Ethernet 100BASE-TIEEE 802.3m standard
Integrated 4B/5B encoder/decoder
Integrated Stream Cipher scrambler/descrambler
Compliant MII interface
Two-wire serial interface management port forconfiguration and control
On-chip 25 MHz crystal oscillator
Interfaces to either AMD's PDT/PDR (AM79865/79866)or Motorola's FCG (MC68836)
Used with ML6673 for 100BASE-TX solutions
44-pin PLCC package



Pinout

  Connection Diagram


Specifications

Supply Voltage (VCC) ............................................... 6.0V
GND................................................ 0.3V to VCC + 0.3V
Logic Inputs .................................. 0.3V to VCC + 0.3V
Input Current per Pin.......................................... ±25mA
Storage Temperature........................... 65 to +150
Package Dissipation at TA = 25 ...................... 750mW
Lead Temperature (soldering 10 sec.) ................. 300




Description

The ML6691* implements the upper portion of the physicallayer for the Fast Ethernet 100BASE-T standard. Functionscontained in the ML6691* include a 4B/5B encoder/decoder, a Stream Cipher scrambler/descrambler, andcollision detect. Additional functions of the ML6691* -accessible through the two-wire MII managementinterface - include full duplex operation, loopback,power down mode, and MII isolation.

The ML6691* is designed to interface to a 100BASE-TEthernet Media Access Controller (MAC) via the MII(Media Independent Interface) on one side, and a100BASE-X PMD transceiver on the other side. Acomplete 100BASE-TX physical layer (PHY) solution isrealized using the ML6691*, the ML6673, and one of theavailable clock recovery/generation devices. A 100BASEFXphysical layer solution is implemented by disabling thescrambler function of the ML6691 and using an external optical PMD.




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