ML6510

The ML6510 (Super PACMan™) is a Programmable Adaptive Clock Manager which offers an ideal solution managing high speed synchronous clock distribution next generation, high speed personal computer and workstation system designs. It provides eight channels deskew buffers that adaptively compensate for clock skew using only a single trace. The input clock of ML6510 can be either TTL or PECL, selected by a bit in the control register. Frequency multiplication or division is possible using M&N divider ratio, within the maximum frequency limit. 0.5X, 1X, 2X and 4X clocks can be easily realized. The ML6510 is implemented using a low jitter PLL with on-chip loop filter.

The ML6510 deskew buffers adaptively compensate for clock skew on PC boards. An internal skew sense circuit is used to sense the skew caused by PCB trace and load delays. The sensing is done by detecting a reflection from the load and the skew is corrected adaptively via a unique phase control delay circuit to provide low load-to-load skew, at the end of PCB traces. Additionally, the ML6510 supports PECL reference clock outputs for use in the generation of clock trees with minimal part-to-part skew. The chip configuration of ML6510 can be programmed to generate the desired output frequency using the internal ROM or an external serial EEPROM or a standard two-wire serial microprocessor interface.