MCM69R536

NOTES:
1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability.
2. Power dissipation capability will be dependent upon package characteristics and use environment. See enclosed thermal impedance data.

The MCM69R536/618 is a 1 megabit synchronous late write fast static RAM designed to provide high performance in secondary cache, ATM switch, Telecom, and other high speed memory applications. The MCM69R618 organized as 64K words by 18 bits, and the MCM69R536 organized as 32K words by 36 bits wide are fabricated in Motorola's high performance silicon gate BiCMOS technology.

The differential CK clock inputs of the MCM69R536 control the timing of read/write operations of the RAM. At the rising edge of the CK clock all addresses, write enables, and synchronous selects are registered. An internal buffer and special logic enable the memory to accept write data on the rising edge of the CK clock a cycle after address and control signals. Read data is driven on the rising edge of the CK clock also.

The RAM of the MCM69R536 uses HSTL inputs and outputs. The adjustable input trip point (Vref) and output voltage (VDDQ) gives the system designer greater flexibility in optimizing system performance. The synchronous write and byte enables allow writing to individual bytes or the entire word.

The impedance of the output buffers of the MCM69R536 is programmable allowing the outputs to match the impedance of the circuit traces which reduces signal reflections.