MCM69L818A

Features:

• Byte Write Control
• Single 3.3 V +10%, 5% Operation
• HSTL - I/O (JEDEC Standard JESD86 Class I)
• HSTL - User Selectable Input TripPoint
• HSTL - Compatible Programmable Impedance Output Drivers
• Register to Latch Synchronous Operation
• Asynchronous Output Enable
• Boundary Scan (JTAG) IEEE 1149.1 Compatible
• Differential Clock Inputs
• Optional x18 or x36 Organization
• MCM69L736A/818A7.5 = 7.5 ns
  MCM69L736A/818A8.5 = 8.5 ns
  MCM69L736A/818A9.5 = 9.5 ns
  MCM69L736A/818A10.5 = 10.5 ns
• 119 Bump, 50 mil (1.27 mm) Pitch, 14 mm x 22 mm Plastic Ball Grid Array (PBGA) Package



Specifications

Rating	Symbol	Value	Unit
Core Supply Voltage	VDD	0.5 to + 4.6	V
Output Supply Voltage	VDDQ	0.5 to VDD + 0.5	V
Voltage On Any Pin	Vin	0.5 to VDD + 0.5	V
Input Current (per I/O)	Iin	± 50	mA
Output Current (per I/O)	Iout	± 70	mA
Power Dissipation (See Note 2)	PD	-	W
Operating Temperature	TA	0 to + 70	°C
Temperature Under Bias	Tbias	10 to + 85	°C
Storage Temperature	Tstg	55 to + 125	°C

Description

The MCM69L736A/818A is a 4M synchronous late write fast static RAM designed to provide high performance in secondary cache and ATM switch,Telecom, and other high speed memory applications. The MCM69L818A (organized as 256K words by 18 bits) and the MCM69L736A (organized as 128K words by 36 bits) are fabricated in Motorola's high performance silicon gate BiCMOS technology.

The differential clock (CK) inputs control the timing of read/write operations of the RAM. At the rising edge of CK, alladdresses, write enables, and synchronous selects are registered. An internal buffer and special logic enable the memory to accept write data on the rising edge of CK a cycle after address and control signals. Read data is available at the falling edge of CK.

The RAM uses HSTL inputs and outputs. The adjustable input trippoint (Vref) and output voltage (VDDQ) gives the system designer greater flexibility in optimizing system performance.

The synchronous write and byte enables allow writing to individual bytes or the entire word.

The impedance of the output buffers is programmable, allowing the outputs to match the impedance of the circuit traces which reduces signal reflections.