MCM69F819

NOTES:
1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability.
2. This is a steadystate DC parameter that is in effect after the power supply has achieved its nominal operating level. Power sequencing is not necessary.
3. Power dissipation capability is dependent upon package characteristics and use environment. See Package Thermal Characteristics.

The MCM69F819 is a 4M bit synchronous fast static RAM designed to provide a burstable, high performance, secondary cache for the PowerPC^TM and other high performance microprocessors. It is organized as 256K words of 18 bits each This device integrates input registers, a 2bit address counter, and high speed SRAM onto a single monolithic circuit for reduced parts count in cache data RAM applications. Synchronous design allows precise cycle control with the use of an external clock (K).

Addresses (SA), data inputs (DQx), and all control signals except output enable (G) and linear burst order (LBO) are clock (K) controlled through positive edgetriggered noninverting registers.

Bursts can be initiated with either ADSP or ADSC input pins. Subsequent burst addresses can be generated internally by the MCM69F819 (burst sequence operates in linear or interleaved mode dependent upon the state of LBO) and controlled by the burst address advance (ADV) input pin.

Write cycles are internally selftimed and are initiated by the rising edge of the clock (K) input. This feature eliminates complex offchip write pulse generation and provides increased timing flexibility for incoming signals.

Synchronous byte write (SBx), synchronous global write (SGW), and synchronous write enable (SW) are provided to allow writes to either individual bytes or to all bytes. The two bytes are designated as "a" and "b". SBa controls DQa and SBb controls DQb. Individual bytes are written if the selected byte writes SBx are  asserted with SW. All bytes are written if either SGW is asserted or if all SBx and SW are asserted.

For read cycles, a flowthrough SRAM allows output data to simply flow freely from the memory array.

The MCM69F819 operates from a 3.3 V core power supply and all outputs operate on a 2.5 V or 3.3 V power supply. All inputs and outputs are JEDEC standard JESD85 compatible.