MCM67Q909

NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability.

The MCM67Q909 is a 4Mbit static random access memory, organized as 512K words of 9 bits. It features separate TTL input and output buffers, which drive 3.3 V output levels, and incorporates input and output registers onboard with high speed SRAM. It also features transparentwrite and data passthrough capabilities.

The synchronous design of the MCM67Q909 allows for precise cycle control with the use of an external single clock (K). The addresses (A0 A18), data input (D0 D8), data output (Q0 Q8), writeenable (W), chipenable (E), and outputenable (G), are registered on the rising edge of clock (K).

The control pins (E, W, G) function of the MCM67Q909 differently in comparison to most synchronous SRAMs. This device will not deselect with E high. The RAM remains active at all times. If E is registered high, the output pins (Q0 Q8) will be driven if G is registered low. The transparent write feature allows the output data to track the input data. E, G, and W must be asserted to perform a transparent write (write and passthrough). The input data is available at the ouputs on the next rising edge of clock (K).

The passthrough function of the MCM67Q909 is always enabled. E high disables the write to the array while allowing a passthrough cycle to occur on the next rising edge of clock (K). Only a registered G high will threestate the outputs. The MCM67Q909 is available in an 86bump surface mount PBGA (Plastic Ball Grid Array) package.