Specifications
|
Rating |
Symbol |
Value |
Unit |
| Power Supply Voltage |
VCC |
0.5 to 7.0 |
V |
Voltage Relative to VSS for Any
Pin Except VCC |
Vin, Vout |
0.5 to VCC + 0.5 |
V |
| Output Current (per I/O) |
Iout |
±30 |
mA |
| Power Dissipation |
PD |
1.6 |
W |
| Temperature Under Bias |
Tbias |
10 to 85 |
°C |
| Ambient Temperature |
TA |
0 to 70 |
°C |
| Storage Temperature |
Tstg |
55 to 125 |
°C |
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability.
DescriptionThe MCM67B618B is a 1,179,648bit synchronous fast static random access memory designed to provide a burstable, highperformance, secondary cache for the i486TM and Pentium microprocessors. The MCM67B618B (organized as 65,536 words by 18 bits) is fabricated using Motorola's highperformance silicongate BiCMOS technology. The device integrates input registers, a 2bit counter, high speed SRAM, and high drive capability outputs onto a single monolithic circuit for reduced parts count implementation of cache data RAM applications. Synchronous design allows precise cycle control with the use of an external clock (K). BiCMOS circuitry reduces the overall power consumption of the integrated functions for greater reliability.
Addresses (A0 A15), data inputs (D0 D17), and all control signals except output enable (G) are clock (K) controlled through positiveedgetriggered noninverting registers.
Bursts can be initiated with either address status processor (ADSP) or address status cache controller (ADSC) input pins. Subsequent burst addresses can be generated internally by the MCM67B618B (burst sequence imitates that of the i486 and Pentium) and controlled by the burst address advance (ADV) input pin. The following pages provide more detailed information on burst controls.
Write cycles of the MCM67B618B are internally selftimed and are initiated by the rising edge of the clock (K) input. This feature eliminates complex offchip write pulse generation and provides increased flexibility for incoming signals.
Dual write enables (LW and UW) are provided to allow individually writeable bytes. LW controls DQ0 DQ8 (the lower bits), while UW controls DQ9 DQ17 (the upper bits).
This MCM67B618B is ideally suited for systems that require wide data bus widths and cache memory. See Figure 2 for applications information.
• Single 5 V ±5% Power Supply
• Fast Access Time: 9 ns Max
• Byte Writeable via Dual Write Enables
• Internal Input Registers (Address, Data, Control)
• Internally SelfTimed Write Cycle
• ADSP, ADSC, and ADV Burst Control Pins
• Asynchronous Output Enable Controlled ThreeState Outputs
• Common Data Inputs and Data Outputs
• 3.3 V I/O Compatible
• High Board Density 52Lead PLCC Package
MCM67B618B Data Sheet
