MCM67B518

Pinout




Specifications

Rating	Symbol	Value	Unit
Power Supply Voltage	VCC	0.5 to + 7.0	V
Voltage Relative to VSS for Any Pin Except VCC	Vin, Vout	0.5 to VCC + 0.5	V
Output Current (per I/O)	Iout	± 30	mA
Power Dissipation	PD	1.5	W
Temperature Under Bias	Tbias	10 to + 85	°C
Operating Temperature	TA	0 to +70	°C
Storage Temperature	Tstg	55 to + 125	°C

Description

The MCM67B518 is a 589,824 bit synchronous fast static random access memory designed to provide a burstable, highperformance, secondary cache for the i486 and Pentium microprocessors. It is organized as 32,768 words of 18 bits, fabricated with Motorola's highperformance silicongate BiCMOS technology. The device integrates input registers, a 2bit counter, high speed SRAM, and high drive capability outputs onto a single monolithic circuit for re duced parts count implementation of cache data RAM applications. Synchro-nous design allows precise cycle control with the use of an external clock (K). BiCMOS circuitry reduces the overall power consumption of the integrated func-
tions for greater reliability.

Addresses (A0 A14), data inputs (D0 D17), and all control signals except output enable (G ) are clock(K)controlled through positiveedgetriggered noninverting registers.