MCM64E836

NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability.

The MCM64E918/MCM64E836 are 8Mbit pipelined burst synchronous late write fast static RAMs designed to provide very high data bandwidth in secondary cache applications. The MCM64E918 (organized as 512K words by 18 bits wide) and the MCM64E836 (organized as 256K words by 36 bits wide) are fabricated in Motorola's high performance silicon gate MOS technology.

The differential clock (CK) inputs control the timing of read/write operations of the RAM. At the rising edge of CK, all addresses and burst control inputs are registered.An internal buffer and special logic enables the memory to accept write data on the rising or rising and falling edges of the clock, a cycle following address and control signals. Read data is driven on the rising or rising and falling edges of the CK clock and is referenced to echo clock (CQ and CQ) outputs.

The MCM64E918/MCM64E836 have HSTL inputs and outputs. The adjustable input trippoint (Vref) and output power supply voltage (VDDQ) gives the system designer greater flexibility in optimizing system performance.

The impedance of the output buffers is programmable, allowing the outputs to match the impedance of the circuit traces, which reduces signal reflections.