MCM63Z819

The ZBT RAM is a 4Mbit synchronous fast static RAM designed to provide Zero Bus TurnaroundE. The ZBT RAM allows 100% use of bus cycles during backtoback read/write and write/read cycles. The MCM63Z737 (organized as 128K words by 36 bits) and the MCM63Z819 (organized as 256K words by 18 bits) are fabricated in Motorola's high performance silicon gate CMOS technology. This device integrates input registers, a 2bit address counter, and high speed SRAM onto a single monolithic circuit for reduced parts count in communication applications. Synchronous design allows precise cycle control with the use of an external clock (CK). CMOS circuitry reduces the overall power consumption of the integrated functions for greater reliability.

Addresses (SA), data inputs (DQ), and all control signals except output enable (G) and linear burst order (LBO) are clock (CK) controlled through positive edgetriggered noninverting registers.

Write cycles of the MCM63Z819 are internally selftimed and are initiated by the rising edge of the clock (CK) input. This feature eliminates complex offchip write pulse generation and provides increased timing flexibility for incoming signals.

For read cycles, a flowthrough SRAM allows output data to simply flow freely from the memory array.
• 3.3 V LVTTL and LVCMOS Compatible
• MCM63Z737/MCM63Z81910 = 10 ns Access/12 ns Cycle (83 MHz)
    MCM63Z737/MCM63Z81911 = 11 ns Access/15 ns Cycle (66 MHz)
    MCM63Z737/MCM63Z81915 = 15 ns Access/20 ns Cycle (50 MHz)
• Selectable Burst Sequencing Order (Linear/Interleaved)
• Internally SelfTimed Write Cycle
• SingleCycle Deselect
• Byte Write Control
• ADV Controlled Burst
• 100Pin TQFP Package