MCM63P531TQ8R

The MCM63P531TQ8R is a 1M bit synchronous fast static RAM designed to provide a burstable, high performance, secondary cache for the 68K Family, PowerPC(TM), and Pentium(TM) microprocessors. The features of MCM63P531TQ8R are: (1)Single 3.3 V + 10%, 5% Power Supply; (2)ADSP, ADSC, and ADV Burst Control Pins; (3)Selectable Burst Sequencing Order (Linear/Interleaved); (4)Internally SelfTimed Write Cycle; (5)Byte Write and Global Write Control; (6)Sleep Mode (ZZ); (7)Intel PBSRAM 2.0 Compliant; (8)SingleCycle Deselect Timing; (9)100 Pin TQFP Package.

The following is about the absolute maximum ratings of MCM63P531TQ8R: (1)Input Timing Measurement Reference Level: 1.5 V; (2)Input Pulse Levels: 0 to 3.0 V; (3)Input Rise/Fall Time: 2 ns; (4)Output Timing Reference Level: 1.5 V; (5)Output Load: See Figure 1 Unless Otherwise Noted.

The electrical characteristics of the MCM63P531TQ8R are: (1)input leakage current(0VVinVDD): ±1A max; (2)output leakage current(0VVinVDD): ±1A max; (3)AC supply current(device selected, cycle timetKHKH min) IOUT=0: TBD max; (4)sleep mode supplu current: 65mA max; (5)output low voltage(IOL=8mA): 0.4V max; (6)output high voltage(IOH=-4mA): 2.4V min.