MCM63P531

Features: * MCM63P5314.5 = 4.5 ns access / 10 ns cycle MCM63P5317 = 7 ns access / 13.3 ns cycle MCM63P5318 = 8 ns access / 15 ns cycle MCM63P5319 = 9 ns access / 16.6 ns cycle* Single 3.3 V + 10%, 5% Power Supply* ADSP, ADSC, and ADV Burst Control Pins* Selectable Burst Sequencing Order (Linear/I...

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SeekIC No. : 004417826 Detail

MCM63P531: Features: * MCM63P5314.5 = 4.5 ns access / 10 ns cycle MCM63P5317 = 7 ns access / 13.3 ns cycle MCM63P5318 = 8 ns access / 15 ns cycle MCM63P5319 = 9 ns access / 16.6 ns cycle* Single 3.3 V + 10%, ...

floor Price/Ceiling Price

Part Number:
MCM63P531
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/11/27

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Product Details

Description



Features:

* MCM63P5314.5 = 4.5 ns access / 10 ns cycle
   MCM63P5317 = 7 ns access / 13.3 ns cycle
   MCM63P5318 = 8 ns access / 15 ns cycle
   MCM63P5319 = 9 ns access / 16.6 ns cycle
* Single 3.3 V + 10%, 5% Power Supply
* ADSP, ADSC, and ADV Burst Control Pins
* Selectable Burst Sequencing Order (Linear/Interleaved)
* Internally SelfTimed Write Cycle
* Byte Write and Global Write Control
* Sleep Mode (ZZ)
* Intel PBSRAM 2.0 Compliant
* SingleCycle Deselect Timing
* 100 Pin TQFP Package



Pinout

  Connection Diagram


Specifications

Input Timing Measurement Reference Level . . . . . . . . . . . . . . .  1.5 V
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  0 to 3.0 V
Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . .  2 ns
Output Timing Reference Level . . . . . . . . . . . . . . . . . . . . . . . . .  1.5 V
Output Load . . . . . . . . . . . . . . See Figure 1 Unless Otherwise Noted



Description

The MCM63P531 is a 1M bit synchronous fast static RAM designed to provide a burstable, high performance, secondary cache for the 68K Family, PowerPC(TM), and Pentium(TM) microprocessors. It is organized as 32K words of 32 bits each, fabricated using high performance silicon gate CMOS technology. This device ntegrates input registers, an output register, a 2bit address counter, and high speed SRAM onto a single monolithic circuit for reduced parts count in cache data RAM applications. Synchronous design allows precise cycle control with the use of an external clock (K). CMOS circuitry reduces the overall power consumption of the integrated functions for greater reliability.


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