MBM29PL160TD-75

Features: Single 3.0 V read, program and erase Minimizes system level power requirementsCompatible with JEDEC-standard commands 2 Uses same software commands as E2 PROMsCompatible with MASK ROM pinouts 48-pin TSOP (I) (Package suffix: PFTN-Normal Bend Type, PFTR-Reversed Bend Type) 44-pin SOP (Pac...

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SeekIC No. : 004414187 Detail

MBM29PL160TD-75: Features: Single 3.0 V read, program and erase Minimizes system level power requirementsCompatible with JEDEC-standard commands 2 Uses same software commands as E2 PROMsCompatible with MASK ROM pino...

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Part Number:
MBM29PL160TD-75
Supply Ability:
5000

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  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/11/27

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Product Details

Description



Features:

Single 3.0 V read, program and erase Minimizes system level power requirements
Compatible with JEDEC-standard commands 2 Uses same software commands as E2 PROMs
Compatible with MASK ROM pinouts 48-pin TSOP (I) (Package suffix: PFTN-Normal Bend Type, PFTR-Reversed Bend Type) 44-pin SOP (Package suffix: PF)
Minimum 100,000 program/erase cycles
High performance 25 ns maximum page access time (75ns maximum random access time)
An 8 words page read mode function
Sector erase architecture One 8K word, two 4K words, one 112K word, and seven 128K words sectors in word mode One 16K byte, two 8K bytes, one 224K byte, and seven 256K bytes sectors in byte mode Any combination of sectors can be concurrently erased. Also supports full chip erase
Boot Code Sector Architecture T = Top sector B = Bottom sector
Embedded Erase Algorithms Automatically pre-programs and erases the chip or any sector TM
Embedded program Algorithms Automatically programs and verifies data at specified address
Data Polling and Toggle Bit feature for detection of program or erase cycle completion
Ready/Busy output (RY/BY) Hardware method for detection of program or erase cycle completion
Automatic sleep mode When addresses remain stable, automatically switches themselves to low power mode
Low VCC write inhibit 2.5 V



Pinout

  Connection Diagram


Specifications

Storage Temperature............................................................................................55°C to +125°C
Ambient Temperature with Power Applied .............................................................40°C to +85°C
Voltage with respect to Ground All pins except A9, OE, and RESET (Note 1)............0.5 V to +5.5 V
VCC (Note 1) ............................................................................................................0.5 V to +4.0 V
A9, OE, and RESET (Note 2).....................................................................................0.5 V to +13.0 V



Description

The MBM29PL160TD-75 is a 16M-bit, 3.0 V-only Flash memory organized as 2M bytes of 8 bits each or 1M words of 16 bits each. The MBM29PL160TD/BD is offered in a 48-pin TSOP (I), and 44-pin SOP packages. The device is designed to be programmed in-system with the standard system 3.0 V VCC supply. 12.0 V VPP and 5.0  V VCC are not required for write or erase operations. The device can also be reprogrammed in standard EPROM programmers.

The standard MBM29PL160TD-75 offers access times of 75 ns and 90 ns, allowing operation of high-speed microprocessors without wait states. To eliminate bus contention the device has separate chip enable (CE), write enable (WE), and output enable (OE) controls. 2

The MBM29PL160TD-75 is pin and command set compatible with JEDEC standard E PROMs. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine which controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is
similar to reading from 5.0 V and 12.0 V Flash or EPROM devices.

The MBM29PL160TD-75 is programmed by executing the program command sequence. This will invoke the Embedded Program Algorithm which is an internal algorithm that automatically times the program pulse widths and verifies proper cell margins. Typically, each sector can be programmed and verified in about 2.0 seconds. Erase is accomplished by executing the erase command sequence. This will invoke the Embedded Erase Algorithm which is an internal algorithm that automatically preprograms the array if it is not already programmed before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margins.

Any individual sector is typically erased and verified in 4.8 second. (If already preprogrammed.)The device also features a sector erase architecture. The sector mode allows each sector to be erased and reprogrammed without affecting other sectors. The MBM29PL160TD-75 is erased when shipped from the factory.

The device features single 3.0 V power supply operation for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. A low VCC detector automatically inhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of DQ7 or by the Toggle Bit feature on DQ6 output pin. Once the end of a program or erase cycle has been comleted, the device internally resets to the read mode.

Fujitsu's Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability, and cost effectiveness. The MBM29PL160TD-75 memory electrically erases all bits within a sector simultaneously via Fowler-Nordhiem tunneling. The bytes/words are programmed one byte/word at a time using the EPROM programming mechanism of hot electron injection.




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