MBM29LV800BE60

Features:

• 0.23 µ µ µ µm Process Technology
• Single 3.0 V Read, Program, and Erase
   Minimized system level power requirements
• Compatible with JEDEC-standard Commands
   Use the same software commands as E²PROMs
• Compatible with JEDEC-standard World-wide Pinouts
   48-pin TSOP (1)  (Package suffix : TN Normal Bend Type)
   48-pin CSOP (Package suffix : PCV)
   48-ball FBGA (Package suffix : PBT)
• Minimum 100,000 Program/Erase Cycles
• High Performance
   70 ns maximum access time
• Sector Erase Architecture
   One 8 Kwords, two 4 Kwords, one 16 Kwords, and fifteen 32 Kwords sectors in word mode
   One 16 Kbytes, two 8 Kbytes, one 32 Kbytes, and fifteen 64 Kbytes sectors in byte mode
   Any combination of sectors can be concurrently erased, and also supports full chip erase.
• Boot Code Sector Architecture
   T = Top sector
   B = Bottom sector
• Embedded Erase^TM* Algorithm
   Automatically pre-programs and erases the chip or any sector.
• Embedded Program^TM* Algorithm
   Automatically writes and verifies data at specified address.
• DataPolling and Toggle Bit Feature for Detection of Program or Erase Cycle Completion
• Ready/Busy Output (RY/ BY)
   Hardware method for detection of program or erase cycle completion
• Automatic Sleep Mode
   When addresses remain stable, MBM29LV800TE/BE automatically switch themselves to low power mode.
• Low VCC Write Inhibit 2.5 V
• Erase Suspend/Resume
   Suspends the erase operation to allow a read data and/or program in another sector within the same device.
• Sector Protection
   Hardware method disables any combination of sectors from program or erase operations.
• Sector Protection Set Function by Extended Sector Protection Command
• Fast Programming Function by Extended Command
• Temporary Sector Unprotection
   Temporary sector unprotection via the RESETpin


Pinout




Specifications

Parameter	Symbol	Rating		Unit
		Min.	Max.
Storage Temperature	Tstg	55	+125	°C
Ambient Temperature with Power Applied	TA	40	+85	°C
Voltage with Respect to Ground All pins except A9, OE, RESET *1, *2	VIN, VOUT	0.5	VCC+0.5	V
Power Supply Voltage *1	VCC	0.5	+5.5	V
A9, OE, and RESET *1, *3	VIN	0.5	+13.0	V

Description

The MBM29LV800BE60 are a 8 M-bit, 3.0 V-only Flash memory organized as 1 M bytes of 8 bits each or 512 Kwords of 16 bits each. The MBM29LV800TE/BE are offered in a 48-pin TSOP (1) , 48-pin CSOP and 48-ball FBGA package. These devices are designed to be programmed in a system with the standard system 3.0 V V_CC supply. 12.0 V V_PP and 5.0 V V_CC are not required for write or erase operations. The devices can also be reprogrammed in standard EPROM programmers.

The standard MBM29LV800BE60 offer access times 60 ns, 70 ns and 90 ns, allowing operation of high-speed microprocessors without wait state. To eliminate bus contention,  the devices have separate chip enable ( CE) ,write enable (WE) , and output enable ( OE) controls.

The MBM29LV800BE60 are pin and command set compatible with JEDEC standard E2PROMs. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine which controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the devices is similar to reading from 5.0 V and 12.0 V Flash or EPROM devices.

The MBM29LV800BE60 are programmed by executing the program command sequence. This will invoke the Embedded Program Algorithm which is an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. Typically, each sector can be programmed and verified in about 0.5 seconds. Erase is accomplished by executing the erase command sequence. This will invoke the Embedded Erase  Algorithm which is an internal algorithm that automatically preprograms the array if it is not already programmed before executing the erase operation. During erase, the devices automatically time the erase pulse widths and verify proper cell margin.

A sector is typically erased and verified in 1.0 second. (If already completely preprogrammed.)

The devices also feature a sector erase architecture. The sector mode allows each sector to be erased and reprogrammed without affecting other sectors. The MBM29LV800BE60 are erased when shipped from the factory.

The devices feature single 3.0 V power supply operation for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. A low V_CC detector automatically inhibits write operations on the loss of power. The end of program or erase is detected by DataPolling of DQ₇, by the Toggle Bit feature on DQ₆, or the RY/ BY output pin. Once the end of a program or erase cycle has been completed, the devices internally resets to the read mode.

The MBM29LV800BE60 also have hardware RESET pins. When this pin is driven low, execution of any Embedded Program Algorithm or Embedded Erase Algorithm is terminated. The internal state machine is thenreset  to the read mode. The RESET pin may be tied to the system reset circuitry. Therefore, if a system reset occurs during  the Embedded Program Algorithm or Embedded Erase Algorithm, the device is automatically reset to the read mode and will have erroneous data stored in the address locations being programmed or erased. These locations need re-writing after the Reset. Resetting the device enables the system's microprocessor to read the boot-up firmware from the Flash memory.

Fujitsu's Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability, and cost effectiveness. The MBM29LV800BE60 memory electrically erase all bits within a sector simultaneously via Fowler-Nordhiem tunneling. The bytes/words are programmed one byte/word at a time using the EPROM programming mechanism of hot electron injection.