Features: • 0.23 mm Process Technology
• Single 3.0 V read, program and erase
Minimizes system level power requirements
• Compatible with JEDEC-standard commands
Uses same software commands as E2PROMs
• Compatible with JEDEC-standard world-wide pinouts
48-pin TSOP (I) (Package suffix: TN-Normal Bend Type, TR-Reversed Bend Type)
48-pin CSOP (Package suffix: PCV)
48-ball FBGA (Package suffix: PBT)
• Minimum 1,000,000 program/erase cycles
• High performance
70 ns maximum access time
• Sector erase architecture
One 8K word, two 4K words, one 16K word, and thirty-one 32K words sectors in word mode
One 16K byte, two 8K bytes, one 32K byte, and thirty-one 64K bytes sectors in byte mode
Any combination of sectors can be concurrently erased. Also supports full chip erase
• Boot Code Sector Architecture
T = Top sector
B = Bottom sector
• Embedded EraseTM Algorithms
Automatically pre-programs and erases the chip or any sectorPinout
Specifications
| Parameter |
Symbol |
Conditions |
Rating |
Unit |
|
- |
Min. |
Max. |
| Storage Temperature |
Tstg |
- |
55 |
+125 |
°C |
Ambient Temperature with
Power Applied |
TA |
- |
40 |
+85 |
°C |
Voltage with Respect to
Ground All pins except A9,
OE, RESET (Note 1) |
VIN, VOUT |
- |
0.5 |
VCC+0.5 |
V |
Power Supply Voltage
(Note 1) |
VCC |
- |
0.5 |
+5.5 |
V |
| A9, OE, and RESET(Note 2) |
VIN |
- |
0.5 |
+13.0 |
V |
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
Notes: 1. Minimum DC voltage on input or I/O pins are 0.5 V. During voltage transitions, inputs may negative overshoot VSS to 2.0 V for periods of up to 20 ns. Maximum DC voltage on output and I/O pins are VCC +0.5 V. During voltage transitions, outputs may positive overshoot to VCC +2.0 V for periods of up to 20 ns.
2. Minimum DC input voltage on A9, OE and RESET pins are 0.5 V. During voltage transitions, A9, OE and RESET pins may negative overshoot VSS to 2.0 V for periods of up to 20 ns. Maximum DC input voltage on A9, OE and RESET pins are +13.0 V which may positive overshoot to 14.0 V for periods of up to 20 ns. when VCC is applied.
3. Minimum DC input voltage on WP/ACC pin is 0.5 V. During voltage transitions, WP/ACC pin may negative overshoot VSS to 2.0 V for periods of up to 20 ns. Maximum DC input voltage on WP/ACC pin iis +10.5V which may positive overshoot to +10.5V for periods of up to 20ns when Vcc is applied.
DescriptionThe MBM29LV160TE/BE is a 4M-bit, 5.0 V-only Flash memory organized as 512K bytes of 8 bits each. The MBM29LV160TE/BE is offered in a 32-pin PLCC and 32-pin TSOP(I) package. This device is designed to be programmed in-system with the standard system 5.0 V VCC supply. A 12.0 V VPP is not required for write or erase operations. The device can also be reprogrammed in standard EPROM programmers.
The standard MBM29LV160TE/BE offers access times 55 ns and 90 ns, allowing operation of high-speed microprocessors without wait states. To eliminate bus contention the device has separate chip enable (CE), write enable (WE), and output enable (OE) controls.
The MBM29LV160TE/BE is pin and command set compatible with JEDEC standard E2PROMs. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine which controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from 12.0 V Flash or EPROM devices.
The MBM29LV160TE/BE is programmed by executing the program command sequence. This will invoke the Embedded Program Algorithm which is an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. Typically, each sector can be programmed and verified in less than 0.5 seconds. Erase is accomplished by executing the erase command sequence. This will invoke the Embedded Erase Algorithm which is an internal algorithm that automatically preprograms the array if it is not already programmed before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin.
Any individual sector is typically erased and verified in 1 second. (If already completely preprogrammed.) The device also features a sector erase architecture.
The sector mode allows for 64K byte sectors of memory to be erased and reprogrammed without affecting other sectors. The MBM29LV160TE/BE is erased when shipped from the factory.
The device features single 5.0 V power supply operation for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. A low VCC detector automatically inhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of DQ7 or by the Toggle Bit feature on DQ6. Once the end of a program or erase cycle has been completed, the device internally resets to the read mode.
Fujitsu's Flash technology combines years of EPROM and E2PROM experience to produce the highest levels of quality, reliability and cost effectiveness. The MBM29LV160TE/BE memory electrically erases the entire chip or all bits within a sector simultaneously via Fowler-Nordheim tunneling. The bytes are programmed one byte at a time using the EPROM programming mechanism of hot electron injection.
MBM29LV160TE/BE Data Sheet
