MBM29LV080A-70

Notes: 1. Minimum DC voltage on input or l/O pins is -0.5 V. During voltage transitions, input or I/O pins
               may undershoot V_SS to -2.0 V for periods of up to 20 ns. Maximum DC voltage on input or l/O pins is
               V_CC + 0.5 V. During voltage transitions, input or I/O pins may overshoot to VCC + 2.0 V for periods
              of up to 20 ns.

           2. Minimum DC input voltage on A9, OE and RESET pins is -0.5 V. During voltage transitions, A9, OE and 
               RESET pins may undershoot V_SS to -2.0 V for periods of up to 20 ns. Voltage difference between input
              and supply voltage (V_IN - V_CC) does not exceed 9.0 V. Maximum DC input voltage on A9, OE and RESET 
              pins is +13.0 V which may overshoot to 14.0 V for periods of up to 20 ns.

WARNING: Semiconductor devices can be  permanently damaged by application of stress (voltage,   current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

The MBM29LV080A-70 is a 16M-bit, 3.0 V-only Flash memory organized as 1M bytes of 8 bits each. The 1M bytes of data is divided into 32 sectors of 64K bytes of flexible erase capability. The 8 bits of data will appear on DQ0 to DQ7. The MBM29LV080A is offered in a 40-pin TSOP (I) package. The device is designed to be programmed in-system with the standard system 3.0 V VCC supply. 12.0 V VPP and 5.0 V VCC are not required for write or erase operations. The device can also be reprogrammed in standard EPROM programmers.

The standard MBM29LV080A-70 offers access times of 70 ns and 120 ns, allowing operation of high-speed microprocessors without wait states. To eliminate bus contention the device has separate chip enable (CE), write enable (WE), and output enable (OE) controls.

The MBM29LV080A-70 is pin and command set compatible with JEDEC standard E2PROMs. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine which controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from 5.0 V and 12.0 V Flash or EPROM devices.

The MBM29LV080A-70 is programmed by executing the program command sequence. This will invoke the Embedded Program Algorithm which is an internal algorithm that automatically times the program pulse widths and verifies proper cell margins. Typically, each sector can be programmed and verified in about 0.5 seconds. Erase is accomplished by executing the erase command sequence. This will invoke the Embedded Erase Algorithm which is an internal algorithm that automatically preprograms the array if it is not already programmed before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margins.

Any individual sector is typically erased and verified in 1.0 second. (If already preprogrammed.)

The device also features a sector erase architecture. The sector mode allows each sector to be erased and reprogrammed without affecting other sectors. The MBM29LV080A-70 is erased when shipped from the factory. Fujitsu has implemented an Erase Suspend feature that enables the user to put erase on hold for any period of time to read data from or program data to a mom-busy sector. Thus, true background erase can be achieved.

MBM29LV080A-70 features single 3.0 V power supply operation for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. A low VCC detector automatically inhibits write operations on the loss of power. The end of program or erase is detected byData Polling of DQ7, by the Toggle Bit feature on DQ6, or the RY/BY output pin. Once the end of a program or erase cycle has been comleted, the device internally resets to the read mode.

The MBM29LV080A-70 also has a hardwareRESET pin. When this pin is driven low, execution of any Embedded Program Algorithm or Embedded Erase Algorithm is terminated. The internal state machine is then reset to the read mode. The RESET pin may be tied to the system reset circuitry. Therefore, if a system reset occurs during the Embedded Program Algorithm or Embedded Erase Algorithm, the device is automatically reset to the read mode and will have erroneous data stored in the address locations being programmed or erased. These locations need re-writing after the Reset. Resetting the device enables the system's microprocessor to read the boot-up firmware from the Flash memory.

Fujitsu's Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability, and cost effectiveness. The MBM29LV080A-70 memory electrically erases all bits within a sector simultaneously via Fowler-Nordhiem tunneling. The bytes are programmed one byte at a time using the EPROM programming mechanism of hot electron injection.